mirror of
https://github.com/WangXuan95/USTC-RVSoC.git
synced 2024-12-24 22:58:56 +08:00
45 lines
1.2 KiB
Systemverilog
45 lines
1.2 KiB
Systemverilog
module DE0Nano_USTCRVSoC_top(
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//////////// CLOCK //////////
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input CLOCK_50,
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//////////// LED, KEY, Switch //////////
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output [7:0] LED,
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//////////// GPIO Header 1 //////////
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input [1:0] GPIO_0_IN,
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inout [33:0] GPIO_0,
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input [1:0] GPIO_1_IN,
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inout [33:0] GPIO_1
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);
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logic vga_red, vga_green, vga_blue;
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assign GPIO_0[31:16] = {{5{vga_blue}},{6{vga_green}},{5{vga_red}}};
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soc_top soc_inst(
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.clk ( CLOCK_50 ),
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.isp_uart_rx ( GPIO_1_IN[0] ),
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.isp_uart_tx ( GPIO_1[0] ),
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.vga_hsync ( GPIO_0[33] ),
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.vga_vsync ( GPIO_0[32] ),
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.vga_red ( vga_red ),
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.vga_green ( vga_green ),
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.vga_blue ( vga_blue )
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);
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// 在开发板的LED上显示ISP-UART和USER-UART的发送灯和接收灯
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assign LED[7:6] = ~{GPIO_1_IN[0],GPIO_1[0]};
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// VGA GND
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assign GPIO_0[12] = 1'b0;
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// 流水灯，指示SoC在运行
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reg [21:0] cnt = 22'h0;
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reg [ 5:0] flow = 6'h0;
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always @ (posedge CLOCK_50) begin
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cnt <= cnt + 22'h1;
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if(cnt==22'h0)
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flow <= {flow[4:0], ~flow[5]};
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end
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assign LED[5:0] = flow;
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endmodule
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