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26 lines
646 B
Systemverilog
26 lines
646 B
Systemverilog
module dual_read_port_ram_32x32( // 32bit*32addr
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input logic clk,
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input logic i_we,
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input logic [ 4:0] i_waddr,
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input logic [31:0] i_wdata,
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input logic [ 4:0] i_raddr1,
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output logic [31:0] o_rdata1,
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input logic [ 4:0] i_raddr2,
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output logic [31:0] o_rdata2
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);
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initial begin o_rdata1 = 0; o_rdata2 = 0; end
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logic [31:0] data_ram_cell [0:31];
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always @ (posedge clk)
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o_rdata1 <= data_ram_cell[i_raddr1];
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always @ (posedge clk)
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o_rdata2 <= data_ram_cell[i_raddr2];
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always @ (posedge clk)
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if(i_we)
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data_ram_cell[i_waddr] <= i_wdata;
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endmodule
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