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24 lines
513 B
Systemverilog
24 lines
513 B
Systemverilog
module soc_top_tb();
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logic clk;
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initial clk = 1'b1;
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always #1 clk = ~clk;
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wire isp_uart_tx, vga_hsync, vga_vsync;
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wire [ 2:0] vga_pixel;
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soc_top soc_inst(
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.clk ( clk ),
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.isp_uart_rx ( 1'b1 ),
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.isp_uart_tx ( isp_uart_tx ),
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.vga_hsync ( vga_hsync ),
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.vga_vsync ( vga_vsync ),
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.vga_red ( vga_pixel[2] ),
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.vga_green ( vga_pixel[1] ),
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.vga_blue ( vga_pixel[0] )
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);
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initial #1000 $stop;
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endmodule
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