mirror of
https://github.com/WangXuan95/USTC-RVSoC.git
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33 lines
1.8 KiB
Plaintext
33 lines
1.8 KiB
Plaintext
#-----------------------------------------------------------
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# Vivado v2017.4 (64-bit)
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# SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017
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# IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
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# Start of session at: Tue Mar 12 00:06:43 2019
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# Process ID: 17980
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# Current directory: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4
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# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent15368 E:\work-Lab\USTCRVSoC\hardware\Vivado\nexys4\USTCRVSoC-nexys4\USTCRVSoC-nexys4.xpr
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# Log file: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/vivado.log
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# Journal file: E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4\vivado.jou
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#-----------------------------------------------------------
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start_gui
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open_project E:/work-Lab/USTCRVSoC/hardware/Vivado/nexys4/USTCRVSoC-nexys4/USTCRVSoC-nexys4.xpr
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update_compile_order -fileset sources_1
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reset_run synth_1
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launch_runs synth_1 -jobs 8
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wait_on_run synth_1
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export_ip_user_files -of_objects [get_files E:/work-Lab/USTCRVSoC/hardware/RTL/core_ex_branch_judge.sv] -no_script -reset -force -quiet
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remove_files E:/work-Lab/USTCRVSoC/hardware/RTL/core_ex_branch_judge.sv
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launch_runs impl_1 -jobs 8
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wait_on_run impl_1
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add_files -norecurse E:/work-Lab/RISCV-Pipline-CPU/1_VerilogSourceCode/1_CPUCore_src/BRAMModule/FakeCache.v
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update_compile_order -fileset sources_1
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export_ip_user_files -of_objects [get_files E:/work-Lab/RISCV-Pipline-CPU/1_VerilogSourceCode/1_CPUCore_src/BRAMModule/FakeCache.v] -no_script -reset -force -quiet
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remove_files E:/work-Lab/RISCV-Pipline-CPU/1_VerilogSourceCode/1_CPUCore_src/BRAMModule/FakeCache.v
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reset_run synth_1
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launch_runs synth_1 -jobs 8
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wait_on_run synth_1
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launch_runs impl_1 -jobs 8
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wait_on_run impl_1
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launch_runs impl_1 -to_step write_bitstream -jobs 8
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wait_on_run impl_1
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