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20 lines
427 B
Systemverilog
20 lines
427 B
Systemverilog
module ram( // 1024B
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input logic clk,
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input logic i_we,
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input logic [ 9:0] i_waddr, i_raddr,
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input logic [ 7:0] i_wdata,
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output logic [ 7:0] o_rdata
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);
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initial o_rdata = 8'h0;
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logic [7:0] data_ram_cell [0:1023] ;
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always @ (posedge clk)
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o_rdata <= data_ram_cell[i_raddr];
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always @ (posedge clk)
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if(i_we)
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data_ram_cell[i_waddr] <= i_wdata;
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endmodule
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