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30 lines
700 B
Systemverilog
30 lines
700 B
Systemverilog
// asm file name: test1.S
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module instr_rom(
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input logic clk, rst_n,
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input logic [13:0] i_addr,
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output logic [31:0] o_data
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);
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localparam INSTR_CNT = 12'd5;
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wire [0:INSTR_CNT-1] [31:0] instr_rom_cell = {
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32'h21006093,
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32'h0210e113,
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32'h00111193,
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32'h5681f213,
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32'h68a06293
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};
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logic [11:0] instr_index;
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logic [31:0] data;
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assign instr_index = i_addr[13:2];
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assign data = (instr_index>=INSTR_CNT) ? 0 : instr_rom_cell[instr_index];
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always @ (posedge clk or negedge rst_n)
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if(~rst_n)
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o_data <= 0;
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else
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o_data <= data;
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endmodule
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