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https://github.com/WangXuan95/USTC-RVSoC.git
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85 lines
2.5 KiB
Systemverilog
85 lines
2.5 KiB
Systemverilog
// Priority : Write Port 1 > Write Port 2 > Write Port 3
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module core_regfile(
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input logic clk, rst_n,
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input logic rd_latch,
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// Read port 1
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input logic i_re1,
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input logic [4:0] i_raddr1,
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output logic [31:0] o_rdata1,
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// Read port 2
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input logic i_re2,
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input logic [4:0] i_raddr2,
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output logic [31:0] o_rdata2,
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// Write port 1
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input logic i_we1,
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input logic [4:0] i_waddr1,
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input logic [31:0] i_wdata1,
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// Write port 2
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input logic i_we2,
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input logic [4:0] i_waddr2,
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input logic [31:0] i_wdata2,
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// Write port 3
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input logic i_we3,
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input logic [4:0] i_waddr3,
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input logic [31:0] i_wdata3
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);
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logic [31:1] [31:0] reg_file_cell = 992'h0;
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// handle regwrite
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always @ (posedge clk or negedge rst_n) begin
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if(~rst_n)
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reg_file_cell <= 992'h0;
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else begin
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if(i_we3 && i_waddr3!=5'h0 && ~(i_we1 && i_waddr1==i_waddr3) && ~(i_we2 && i_waddr2==i_waddr3) )
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reg_file_cell[i_waddr3] <= i_wdata3;
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if(i_we2 && i_waddr2!=5'h0 && ~(i_we1 && i_waddr1==i_waddr2) )
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reg_file_cell[i_waddr2] <= i_wdata2;
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if(i_we1 && i_waddr1!=5'h0 )
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reg_file_cell[i_waddr1] <= i_wdata1;
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end
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end
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always @ (posedge clk or negedge rst_n) begin
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if(~rst_n)
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o_rdata1 <= 0;
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else begin
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if(rd_latch) begin
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o_rdata1 <= o_rdata1;
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end else if(i_re1 && i_raddr1!=5'h0) begin
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if (i_we1 && i_raddr1==i_waddr1)
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o_rdata1 <= i_wdata1;
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else if(i_we2 && i_raddr1==i_waddr2)
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o_rdata1 <= i_wdata2;
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else if(i_we3 && i_raddr1==i_waddr3)
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o_rdata1 <= i_wdata3;
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else
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o_rdata1 <= reg_file_cell[i_raddr1];
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end else
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o_rdata1 <= 0;
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end
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end
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always @ (posedge clk or negedge rst_n) begin
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if(~rst_n)
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o_rdata2 <= 0;
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else begin
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if(rd_latch) begin
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o_rdata2 <= o_rdata2;
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end else if(i_re2 && i_raddr2!=5'h0) begin
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if (i_we1 && i_raddr2==i_waddr1)
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o_rdata2 <= i_wdata1;
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else if(i_we2 && i_raddr2==i_waddr2)
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o_rdata2 <= i_wdata2;
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else if(i_we3 && i_raddr2==i_waddr3)
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o_rdata2 <= i_wdata3;
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else
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o_rdata2 <= reg_file_cell[i_raddr2];
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end else
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o_rdata2 <= 0;
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end
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end
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endmodule
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