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22 lines
526 B
Systemverilog
22 lines
526 B
Systemverilog
module soc_top_tb();
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logic clk, rst_n;
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initial clk = 1'b1;
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always #1 clk = ~clk;
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wire vga_vsync, vga_hsync, user_uart_tx, isp_uart_tx;
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wire [15:0] vga_pixel;
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soc_top soc_inst(
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.clk ( clk ),
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.isp_uart_rx ( 1'b1 ),
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.isp_uart_tx ( isp_uart_tx ),
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.user_uart_rx ( 1'b1 ),
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.user_uart_tx ( user_uart_tx),
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.vga_hsync ( vga_hsync ),
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.vga_vsync ( vga_vsync ),
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.vga_pixel ( vga_pixel )
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);
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endmodule
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