basic_verilog/Advanced Synthesis Cookbook/random/lfsr_test.v

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module lfsr_test ();

parameter WIDTH = 20;

reg clk, rst, fail;
integer cycles;

wire [WIDTH-1:0] out;

lfsr l (.clk(clk),.rst(rst),.out(out));
	defparam l .WIDTH = WIDTH;

initial begin 
	rst = 0;
	clk = 0;
	fail = 0;
	#10 rst = 1;
	#10 rst = 0;
	cycles = 0;
end

always @(posedge clk) begin
  cycles = cycles + 1;
  if (cycles == (1 << WIDTH)) begin
	if (out != 0) begin
		$display ("Failed to return to zero");
	end
	else begin
		if (!fail) $display ("PASS");
	end
	$stop();
  end
end

always @(negedge clk) begin
  if ((cycles != (1 << WIDTH)-1) && out == 0) begin
	$display ("Early return to zero");
	fail = 1;
  end
end 

always begin
	#1000 clk = ~clk;	
end

endmodule