mirror of
https://github.com/pConst/basic_verilog.git
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72 lines
1.8 KiB
Plaintext
72 lines
1.8 KiB
Plaintext
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/* Symbol Table */
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// _loop = LABEL: 7
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// binary = CONSTANT: 9
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// character = CONSTANT: 97
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// decimal = CONSTANT: 123
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// func = LABEL: 14
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// hexadecimal = CONSTANT: 202
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// ic = REGISTER: 21
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// int = LABEL: 1023
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// isr = LABEL: 17
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// loop = LABEL: 7
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// loop_1 = LABEL: 11
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// octal = CONSTANT: 63
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// r0 = REGISTER: 0
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// r1 = REGISTER: 1
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// s0 = REGISTER: 0
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// s1 = REGISTER: 1
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// s2 = REGISTER: 2
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// s3 = REGISTER: 3
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// s4 = REGISTER: 4
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// s5 = REGISTER: 5
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// s6 = REGISTER: 6
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// s7 = REGISTER: 7
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// s8 = REGISTER: 8
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// s9 = REGISTER: 9
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// sA = REGISTER: 10
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// sB = REGISTER: 11
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// sC = REGISTER: 12
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// sD = REGISTER: 13
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// sE = REGISTER: 14
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// sF = REGISTER: 15
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// start = LABEL: 0
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/* Program Code */
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// #1: ; test3.psm
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// #3: register(r0,0) ; register 0
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// #4: register(r1,1) ; register 1
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// #5: register(ic,21) ; isr register
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// #7: constant(binary,9) ; binary value
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// #8: constant(octal,63) ; octal value
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// #9: constant(decimal,123) ; decimal value
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// #10: constant(hexadecimal,202) ; hexadecimal value
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// #11: constant(character,97) ; character value
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// @000 #14: [start]
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00009 // @000 #15: load(r0,binary)
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001fe // @001 #16: load(r1,254)
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01500 // @002 #17: load(ic,0)
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00200 // @003 #19: load(s2,0)
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19200 // @004 #20: add(s2,r0)
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1b210 // @005 #21: addcy(s2,r1)
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3c001 // @006 #22: interrupt(enable)
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// @007 #24: [loop] ; first name
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// @007 #25: [_loop]
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01320 // @007 #26: load(s3,s2) ; load it
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1e301 // @008 #27: subcy(s3,1)
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3580b // @009 #28: jump(c,loop_1)
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2020a // @00a #29: srx(s2)
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// @00b #31: [loop_1]
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20304 // @00b #31: slx(s3)
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3000e // @00c #32: call(func)
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34007 // @00d #33: jump(loop)
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// @00e #35: [func] ; function
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180ca // @00e #36: add(s0,hexadecimal)
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1e07b // @00f #37: subcy(s0,decimal)
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2a000 // @010 #38: return
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// @011 #40: [isr]
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19501 // @011 #41: add(ic,1)
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38001 // @012 #42: returni(enable)
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// @013 #44: [int]
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@3ff // #44: address(1023)
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34011 // @3ff #45: jump(isr)
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