basic_verilog/Advanced Synthesis Cookbook/ethernet_fec/fec_gen.v

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// baeckler - 12-04-2008
// Ethernet 10/40/100G style FEC insertion + PN2112 scramble

module fec_gen (
	input clk,arst,
	input [31:0] din,
	input parity_sel,	// the next tick's dout is to be the parity word
	output reg [31:0] dout
);

`include "reverse_32.inc"

///////////////////////////
// parity workhorse

reg [31:0] parity;
wire [31:0] next_parity;

fec_parity fs (.c(parity),.d(din),.co(next_parity));

///////////////////////////
// pseudo noise scrambler
wire [31:0] pn_val_w;
reg [31:0] pn_val;
reg [6:0] pn_cntr;

pn2112_table pn (
	.din(pn_cntr),
	.dout(pn_val_w)
);

always @(posedge clk) begin
	if (arst) begin
		pn_val <= 0;
		pn_cntr <= 0;
	end
	else begin
		pn_val <= pn_val_w;
		if (parity_sel) begin
			pn_cntr <= 1'b1;
			pn_val <= 32'hffffffff;
		end
		else begin
			if (pn_cntr == 7'd65) pn_cntr <= 0;
			else pn_cntr <= pn_cntr + 1'b1;
		end
	end
end

///////////////////////////
// output register

always @(posedge clk or posedge arst) begin
    if (arst) begin
		parity <= 0;
		dout <= 0;		
	end
    else begin
		parity <= parity_sel ? 32'b0 : next_parity;
		dout <= (parity_sel ? reverse_32(parity) : din) ^ pn_val;
	end
end

endmodule