basic_verilog/Advanced Synthesis Cookbook/arithmetic/addsub.v

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module addsub (sub,a,b,o);

parameter WIDTH = 16;
parameter METHOD = 1;

input sub;
input [WIDTH-1:0] a,b;
output [WIDTH:0] o;

generate
  if (METHOD == 0) begin
    // generic style
    assign o = sub ? (a - b) : (a + b);
  end
  else if (METHOD == 1) begin
    // Hardware implementation with XORs in front of a
	// carry chain.
	wire [WIDTH+1:0] tmp;
	assign tmp = {1'b0,a,sub} + {sub,{WIDTH{sub}} ^ b,sub};
	assign o = tmp[WIDTH+1:1];
  end
endgenerate

endmodule

/////////////////////////////////////

module addsub_tb ();
parameter WIDTH = 16;

reg [WIDTH-1:0] a,b;
reg sub,fail;
wire [WIDTH:0] ox,oy;

initial begin
  a = 0;
  b = 0;
  fail = 0;
  #100000 if (!fail) $display ("PASS");
  $stop();
end

addsub x (.a(a),.b(b),.sub(sub),.o(ox));
  defparam x .WIDTH = WIDTH;
  defparam x .METHOD = 0;

addsub y (.a(a),.b(b),.sub(sub),.o(oy));
  defparam y .WIDTH = WIDTH;
  defparam y .METHOD = 1;

always begin
  #50 a = $random;
  b = $random;
  sub = $random;
  #50 
  if (ox !== oy) begin
    $display ("Mismatch at time %d",$time);
    fail = 1;
  end
end
endmodule