basic_verilog/Advanced Synthesis Cookbook/random/rand_test.v

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module rand_test ();

reg clk, rst, reseed;

wire [15:0] out;
reg [31:0] seed_val;

c_rand c (.clk(clk),.rst(rst),.reseed(reseed),.seed_val(seed_val),.out(out));

initial begin 
	rst = 0;
	clk = 0;
	seed_val = 32'd1234;
	#10 rst = 1;
	#10 rst = 0;
	#10 reseed = 1;
end

always @(negedge clk) begin
  reseed = 0;
  $display ("%x",out);
end

always begin
	#1000 clk = ~clk;	
end

endmodule