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https://github.com/pConst/basic_verilog.git
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38 lines
909 B
Coq
38 lines
909 B
Coq
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//--------------------------------------------------------------------------------
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// SetReset.v
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// Konstantin Pavlov, pavlovconst@gmail.com
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//--------------------------------------------------------------------------------
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// INFO --------------------------------------------------------------------------------
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// <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> SR-<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>.
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// <EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>. <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD>.
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module SetReset(clk,nrst,s,r,q,nq);
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input wire clk;
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input wire nrst;
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input wire [(WIDTH-1):0] r;
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input wire [(WIDTH-1):0] s;
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output reg [(WIDTH-1):0] q = 0; // also "present state"
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output wire [(WIDTH-1):0] nq;
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parameter WIDTH = 1;
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assign
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nq[(WIDTH-1):0] = ~q[(WIDTH-1):0];
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integer i;
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always @ (posedge clk) begin
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if (~nrst) begin
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q <= 0;
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end
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else begin
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for (i=0; i<WIDTH; i=i+1) begin
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if (s[i]) q[i] = 1;
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if (r[i]) q[i] = 0;
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end
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end // else
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end
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endmodule
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