basic_verilog/Advanced Synthesis Cookbook/arbitration/bitscan_tb.v

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module bitscan_tb ();
parameter WIDTH = 16;
reg [WIDTH-1:0] req;
wire [WIDTH-1:0] sel;

bitscan b (.req(req),.sel(sel));
  defparam b .WIDTH = WIDTH;

initial begin
  req = 16'h8000;
end

integer n;
reg [WIDTH-1:0] result;
reg fail = 0;

always begin 
  #100 req = $random & $random & $random;
  #10 
  result = 0;
  for (n=0; n<WIDTH; n=n+1)
  begin
	if (req[n] == 1'b1) begin
		result[n] = 1'b1;
		n = WIDTH;
	end
  end
  #10 if (sel !== result) begin
	$display ("Mismatch at time %d",$time);
	fail = 1'b1;
	$stop();
  end
end

initial begin
	#1000000 if (!fail) $display ("PASS");
	$stop();
end

endmodule