mirror of
https://github.com/pConst/basic_verilog.git
synced 2025-02-04 07:12:56 +08:00
415 lines
14 KiB
Coq
415 lines
14 KiB
Coq
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// Copyright 2007 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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// baeckler - 04-10-2006
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// an 8b10b decoder, based on files from Martin R and IBM paper
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module decoder_8b10b (
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clk,
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rst,
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din_ena, // 10b data ready
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din_dat, // 10b data input
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din_rd, // running disparity input
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dout_val, // data out valid
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dout_dat, // data out
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dout_k, // special code
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dout_kerr, // coding mistake detected
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dout_rderr, // running disparity mistake detected
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dout_rdcomb, // running disparity output (comb)
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dout_rdreg // running disparity output (reg)
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);
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parameter RDERR = 1;
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parameter KERR = 1;
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// method = 0 is generic for comparison / test
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// method = 1 is speed optimized
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parameter METHOD = 1;
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input clk;
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input rst;
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input din_ena;
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input [9:0] din_dat;
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input din_rd;
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output dout_val;
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output[7:0] dout_dat;
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output dout_k;
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output dout_kerr;
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output dout_rderr;
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output dout_rdcomb;
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output dout_rdreg;
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//reg [9:0] din_dat;
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reg dout_val;
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reg [7:0] dout_dat;
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reg dout_k;
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reg dout_kerr;
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reg dout_rderr;
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reg dout_rdreg;
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wire a = din_dat[0];
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wire b = din_dat[1];
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wire c = din_dat[2];
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wire d = din_dat[3];
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wire e = din_dat[4];
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wire i = din_dat[5];
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wire f = din_dat[6];
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wire g = din_dat[7];
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wire h = din_dat[8];
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wire j = din_dat[9];
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//classification
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wire P04 = (!a & !b & !c & !d);
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wire P13 = (!a & !b & !c & d) | (!a & !b & c & !d) | (!a & b & !c & !d) | (a & !b & !c & !d);
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wire P22 = (!a & !b & c & d) | (!a & b & c & !d) | (a & b & !c & !d) | (a & !b & c & !d) | (a & !b & !c & d) | (!a & b & !c & d);
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wire P31 = (a & b & c & !d) | (a & b & !c & d) | (a & !b & c & d) | (!a & b & c & d);
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wire P40 = (a & b & c & d);
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////////////////////////////////////////////////
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// data outputs
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////////////////////////////////////////////////
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wire A = (P22 & !b & !c & !(e^i)) ? !a :
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(P31 & i) ? !a :
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(P13 & d & e & i) ? !a :
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(P22 & !a & !c & !(e^i)) ? !a :
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(P13 & !e) ? !a :
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(a & b & e & i) ? !a :
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(!c & !d & !e & !i) ? !a :
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a;
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wire B = (P22 & b & c & !(e^i)) ? !b :
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(P31 & i) ? !b :
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(P13 & d & e & i) ? !b :
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(P22 & a & c & !(e^i)) ? !b :
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(P13 & !e) ? !b :
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(a & b & e & i) ? !b :
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(!c & !d & !e & !i) ? !b :
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b;
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wire C = (P22 & b & c & !(e^i)) ? !c :
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(P31 & i) ? !c :
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(P13 & d & e & i) ? !c :
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(P22 & !a & !c & !(e^i)) ? !c :
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(P13 & !e) ? !c :
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(!a & !b & !e & !i) ? !c :
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(!c & !d & !e & !i) ? !c :
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c;
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wire D = (P22 & !b & !c & !(e^i)) ? !d :
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(P31 & i) ? !d :
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(P13 & d & e & i) ? !d :
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(P22 & a & c & !(e^i)) ? !d :
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(P13 & !e) ? !d :
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(a & b & e & i) ? !d :
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(!c & !d & !e & !i) ? !d :
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d;
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wire E = (P22 & !b & !c & !(e^i)) ? !e :
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(P13 & !i) ? !e :
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(P13 & d & e & i) ? !e :
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(P22 & !a & !c & !(e^i)) ? !e :
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(P13 & !e) ? !e :
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(!a & !b & !e & !i) ? !e :
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(!c & !d & !e & !i) ? !e :
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e;
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wire F = (f & h & j) ? !f :
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(!c & !d & !e & !i & (h^j)) ? !f :
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(!f & !g & h & j) ? !f :
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(f & g & j) ? !f :
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(!f & !g & !h) ? !f :
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(g & h & j) ? !f :
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f;
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wire G = (!f & !h & !j) ? !g :
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(!c & !d & !e & !i & (h^j)) ? !g :
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(!f & !g & h & j) ? !g :
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(f & g & j) ? !g :
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(!f & !g & !h) ? !g :
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(!g & !h & !j) ? !g :
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g;
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wire H = (f & h & j) ? !h :
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(!c & !d & !e & !i & (h^j)) ? !h :
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(!f & !g & h & j) ? !h :
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(f & g & j) ? !h :
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(!f & !g & !h) ? !h :
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(!g & !h & !j) ? !h :
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h;
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wire K = (c & d & e & i) |
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(!c & !d & !e & !i) |
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(P13 & !e & i & g & h & j) |
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(P31 & e & !i & !g & !h & !j);
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////////////////////////////////////////////////
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//running disparity - generate and err check
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////////////////////////////////////////////////
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wire rd1n = (P04) ? 1 :
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(P13 & !(e & i)) ? 1 :
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(P22 & !e & !i) ? 1 :
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(P13 & d & e & i) ? 1 :
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0 /* synthesis keep */;
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wire rd1p = (P40) ? 1 :
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(P31 & !(!e & !i)) ? 1 :
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(P22 & e & i) ? 1 :
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(P31 & !d & !e & !i) ? 1 :
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0 /* synthesis keep */;
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wire rd1e = (P13 & !d & e & i) ? 1 :
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(P22 & (e ^ i)) ? 1 :
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(P31 & d & !e & !i) ? 1 :
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0 /* synthesis keep */;
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wire rd1_err = (!din_rd & rd1n) | (din_rd & rd1p);
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/////////////////////////////
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// factored rd1 generation
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/////////////////////////////
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wire [63:0] rd1_when_din_rd_0_mask = 64'hffe8e880e8808000;
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wire rd1_when_din_rd_0 = rd1_when_din_rd_0_mask[din_dat[5:0]] /* synthesis keep */;
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wire [63:0] rd1_when_din_rd_1_mask = 64'hfffefee8fee8e800;
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wire rd1_when_din_rd_1 = rd1_when_din_rd_1_mask[din_dat[5:0]] /* synthesis keep */;
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wire rd1 = din_rd ? rd1_when_din_rd_1 : rd1_when_din_rd_0;
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wire rd2n = (!f & !g & !h) ? 1 :
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(!f & !g & !j) ? 1 :
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(!f & !h & !j) ? 1 :
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(!g & !h & !j) ? 1 :
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(!f & !g & h & j) ? 1 :
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0 /* synthesis keep */;
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wire rd2p = (f & g & h) ? 1 :
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(f & g & j) ? 1 :
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(f & h & j) ? 1 :
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(g & h & j) ? 1 :
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(f & g & !h & !j) ? 1 :
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0 /* synthesis keep */;
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wire rd2e = ((f ^ g) & (h ^ j)) ? 1 :
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0;
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wire rd2_err = (!rd1 & rd2n) | (rd1 & rd2p);
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// these two conditions appear in rd2p and rd2n with the
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// opposite associated rdcomb output.
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wire dout_rdcomb_special = (!f & !g & h & j) |
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( f & g & !h & !j) /* synthesis keep */;
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wire dout_rdcomb = (rd2p) ? !dout_rdcomb_special :
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(rd2n) ? dout_rdcomb_special :
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rd1;
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////////////////////////////////////////////////
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// K error check - this is by far the most
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// complex expression in the decoder.
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// It appears to require depth 3. Please let
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// me know if you identify a depth 2 mapping.
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////////////////////////////////////////////////
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wire k_err;
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generate
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if (METHOD == 0) begin
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assign k_err = //5b6b errors
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(P04) ? 1 :
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(P13 & !e & !i) ? 1 :
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(P31 & e & i) ? 1 :
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(P40) ? 1 :
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//3b4b errors
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( f & g & h & j) ? 1 :
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(!f & !g & !h & !j) ? 1 :
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//any 2nd phase rd error, except if rd1 is even
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(rd2_err & !rd1e) ? 1 :
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// + some odd ones, dx.7 - specials ...
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// d11.7,d13.7,d14.7,d17.7,d18.7,d20.7 use 1000/0111
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// k23.7,k27.7,k29.7,k30.7 are legal use 1000/0111
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// other x.7 use 0001/1110
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// P22 & xxxx01 1110 - ok, d12.7
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// P22 & xxxx10 1110 - ok, d28.7
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// P22 & 011000 1110 - ok, d0.7
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// P22 & 101000 1110 - ok, d15.7
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// P22 & 100100 1110 - ok, d16.7
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// P22 & 001100 1110 - ok, d24.7
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// P22 & 010100 1110 - ok, d31.7
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// P22 & 110000 1110 - illegal
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// xxxx11 1110 - illegal
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( a & b & !c & !d & !e & !i & f & g & h & !j) ? 1 :
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( e & i & f & g & h & !j) ? 1 :
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// P22 & xxxx01 0001 - ok, d6.7
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// P31 & xxxx01 0001 - ok, d1.7
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// P31 & xxxx10 0001 - ok, d23.7
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// P22 & xxxx10 0001 - ok, d19.7
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// P13 & xxxx11 0001 - ok, d7.7
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// 110011 0001 - ok, d24.7
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// 101011 0001 - ok, d31.7
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// 011011 0001 - ok, d16.7
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// 100111 0001 - ok, d0.7
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// 010111 0001 - ok, d15.7
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// 001111 0001 - illegal
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// xxxx00 0001 - illegal
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(!a & !b & c & d & e & i & !f & !g & !h & j) ? 1 :
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( !e & !i & !f & !g & !h & j) ? 1 :
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// 110000 0111 - ok, k28.7
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// P13 & xxxx01 0111 = ok, kxx.7
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// 100011 0111 = ok, d17.7
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// 010011 0111 = ok, d18.7
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// 001011 0111 = ok, d20.7
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// 000111 0111 = illegal (rderr)
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// else xxxxxx 0111 - illegal
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(!(P22 & !c & !d) & !e & !i & !f & g & h & j) ? 1 :
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(!(P13) & !e & i & !f & g & h & j) ? 1 :
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(!(P13 & (a | b | c)) & e & i & !f & g & h & j) ? 1 :
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( e & !i & !f & g & h & j) ? 1 :
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// 001111 1000 - ok, k28.7
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// P31 & xxxx10 1000 = ok, kxx.7
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// 110100 1000 - ok, d11.7
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// 101100 1000 - ok, d13.7
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// 011100 1000 - ok, d14.7
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// 111000 1000 - illegal (rderr)
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// else xxxxxx 1000 - illegal
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(!(P22 & c & d) & e & i & f & !g & !h & !j) ? 1 :
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(!(P31) & e & !i & f & !g & !h & !j) ? 1 :
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(!(P31 & (!a | !b | !c)) & !e & !i & f & !g & !h & !j) ? 1 :
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( !e & i & f & !g & !h & !j) ? 1 :
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0;
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end
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else if (METHOD == 1) begin
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/////////////////////////////////////
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// use the upper and lower portions only
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// to identify definite errors
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/////////////////////////////////////
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wire [63:0] kerr_mask_ai = 64'h6881800180018117;
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wire [63:0] kerr_mask_ej = 64'hf20000018000004f;
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wire kerr_out_ai = kerr_mask_ai[din_dat[5:0]] /* synthesis keep */;
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wire kerr_out_ej = kerr_mask_ej[din_dat[9:4]] /* synthesis keep */;
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wire rd2_err_lc = rd2_err /* synthesis keep */;
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wire kerr6,kerr7,kerr8,kerr9,kerr_remainder;
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stratixii_lcell_comb kerr6_I (
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.datab(!din_dat[7]),
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.datac(!din_dat[6]),
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.datad(!din_dat[8]),
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.datae(!din_dat[9]),
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.dataa(1'b1),.dataf(1'b1),.datag(1'b1),
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.cin(1'b1),.sharein(1'b0),.sumout(),.cout(),.shareout(),
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.combout(kerr6 ));
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defparam kerr6_I .shared_arith = "off";
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||
|
|
defparam kerr6_I .extended_lut = "off";
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||
|
|
defparam kerr6_I .lut_mask = 64'h0C0000300C000030;
|
||
|
|
|
||
|
|
stratixii_lcell_comb kerr7_I (
|
||
|
|
.dataa(!din_dat[3]),
|
||
|
|
.datab(!din_dat[7]),
|
||
|
|
.datac(!din_dat[6]),
|
||
|
|
.datad(!din_dat[8]),
|
||
|
|
.datae(!din_dat[9]),
|
||
|
|
.dataf(1'b1),.datag(1'b1),
|
||
|
|
.cin(1'b1),.sharein(1'b0),.sumout(),.cout(),.shareout(),
|
||
|
|
.combout(kerr7 ));
|
||
|
|
defparam kerr7_I .shared_arith = "off";
|
||
|
|
defparam kerr7_I .extended_lut = "off";
|
||
|
|
defparam kerr7_I .lut_mask = 64'h0002403000024030;
|
||
|
|
|
||
|
|
stratixii_lcell_comb kerr8_I (
|
||
|
|
.dataa(!din_dat[0]),
|
||
|
|
.datab(!din_dat[1]),
|
||
|
|
.datac(!din_dat[2]),
|
||
|
|
.datad(!din_dat[4]),
|
||
|
|
.datae(!din_dat[3]),
|
||
|
|
.dataf(1'b1),.datag(1'b1),
|
||
|
|
.cin(1'b1),.sharein(1'b0),.sumout(),.cout(),.shareout(),
|
||
|
|
.combout(kerr8 ));
|
||
|
|
defparam kerr8_I .shared_arith = "off";
|
||
|
|
defparam kerr8_I .extended_lut = "off";
|
||
|
|
defparam kerr8_I .lut_mask = 64'h6868960868689608;
|
||
|
|
|
||
|
|
stratixii_lcell_comb kerr9_I (
|
||
|
|
.dataa(!din_dat[0]),
|
||
|
|
.datab(!din_dat[1]),
|
||
|
|
.datac(!din_dat[2]),
|
||
|
|
.datad(!din_dat[4]),
|
||
|
|
.datae(!din_dat[3]),
|
||
|
|
.dataf(1'b1),.datag(1'b1),
|
||
|
|
.cin(1'b1),.sharein(1'b0),.sumout(),.cout(),.shareout(),
|
||
|
|
.combout(kerr9 ));
|
||
|
|
defparam kerr9_I .shared_arith = "off";
|
||
|
|
defparam kerr9_I .extended_lut = "off";
|
||
|
|
defparam kerr9_I .lut_mask = 64'h1001161E1001161E;
|
||
|
|
|
||
|
|
stratixii_lcell_comb kerr_rem_I (
|
||
|
|
.dataa(!din_dat[5]),
|
||
|
|
.datab(!kerr6 ),
|
||
|
|
.datac(!kerr7 ),
|
||
|
|
.datad(!din_dat[4]),
|
||
|
|
.datae(!kerr8 ),
|
||
|
|
.dataf(!kerr9 ),
|
||
|
|
.datag(1'b1),
|
||
|
|
.cin(1'b1),.sharein(1'b0),.sumout(),.cout(),.shareout(),
|
||
|
|
.combout(kerr_remainder ));
|
||
|
|
defparam kerr_rem_I .shared_arith = "off";
|
||
|
|
defparam kerr_rem_I .extended_lut = "off";
|
||
|
|
defparam kerr_rem_I .lut_mask = 64'h2331223029110325;
|
||
|
|
|
||
|
|
assign k_err = kerr_out_ai | kerr_out_ej |
|
||
|
|
rd2_err_lc & !rd1e |
|
||
|
|
kerr_remainder;
|
||
|
|
end
|
||
|
|
endgenerate
|
||
|
|
|
||
|
|
////////////////////////////////////////////////
|
||
|
|
// output registers
|
||
|
|
////////////////////////////////////////////////
|
||
|
|
always @(posedge clk or posedge rst)
|
||
|
|
begin
|
||
|
|
if (rst)
|
||
|
|
begin
|
||
|
|
dout_k <= 0;
|
||
|
|
dout_val <= 0;
|
||
|
|
dout_dat <= 0;
|
||
|
|
dout_rdreg <= 0;
|
||
|
|
dout_rderr <= 0;
|
||
|
|
dout_kerr <= 0;
|
||
|
|
end
|
||
|
|
else
|
||
|
|
begin
|
||
|
|
dout_val <= 0;
|
||
|
|
if (din_ena)
|
||
|
|
begin
|
||
|
|
dout_k <= K;
|
||
|
|
dout_val <= din_ena;
|
||
|
|
dout_dat <= {H,G,F,E,D,C,B,A};
|
||
|
|
dout_rdreg <= dout_rdcomb;
|
||
|
|
dout_rderr <= (RDERR) ? (rd1_err | rd2_err) : 0;
|
||
|
|
dout_kerr <= (KERR) ? k_err : 0;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
|
||
|
|
endmodule
|