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65 lines
2.1 KiB
Coq
65 lines
2.1 KiB
Coq
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// Copyright 2007 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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// baeckler - 11-14-2005
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// counter with unstable count enable signal based
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// on ring oscillator.
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module ring_counter (clk,rst,out);
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parameter DELAY = 100;
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input clk,rst;
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output [15:0] out;
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wire [DELAY-1:0] delay_line /* synthesis keep */;
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reg [15:0] cntr;
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reg sync0;
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reg wobble;
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// unstable ring oscillator
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genvar i;
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generate
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for (i=1; i<DELAY; i=i+1)
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begin : del
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assign delay_line [i] = delay_line[i-1];
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end
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endgenerate
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assign delay_line [0] = !delay_line [DELAY-1];
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// sync it over to the input clock
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always @(posedge clk) begin
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sync0 <= delay_line[0];
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wobble <= sync0;
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end
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// count when the wobbly oscillator is high
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always @(posedge clk or posedge rst) begin
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if (rst) cntr <= 0;
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else if (wobble) cntr <= cntr + 1;
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end
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assign out = cntr;
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endmodule
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