mirror of
https://github.com/pConst/basic_verilog.git
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44 lines
978 B
Plaintext
44 lines
978 B
Plaintext
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/* Symbol Table */
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// func = LABEL: 7
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// irq = LABEL: 1023
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// isr = LABEL: 9
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// loop = LABEL: 4
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// s0 = REGISTER: 0
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// s1 = REGISTER: 1
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// s2 = REGISTER: 2
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// s3 = REGISTER: 3
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// s4 = REGISTER: 4
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// s5 = REGISTER: 5
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// s6 = REGISTER: 6
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// s7 = REGISTER: 7
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// s8 = REGISTER: 8
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// s9 = REGISTER: 9
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// sA = REGISTER: 10
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// sB = REGISTER: 11
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// sC = REGISTER: 12
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// sD = REGISTER: 13
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// sE = REGISTER: 14
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// sF = REGISTER: 15
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// start = LABEL: 0
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/* Program Code */
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@000 // #2: address(0)
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// @000 #3: [start]
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00000 // @000 #4: load(s0,0)
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00e00 // @001 #5: load(sE,0)
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00f00 // @002 #6: load(sF,0)
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3c001 // @003 #7: interrupt(enable)
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// @004 #9: [loop]
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1a0f0 // @004 #10: addcy(s0,240)
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31c07 // @005 #11: call(nc,func)
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34004 // @006 #12: jump(loop)
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// @007 #14: [func]
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18e03 // @007 #15: add(sE,3)
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2a000 // @008 #16: return
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// @009 #18: [isr]
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1af01 // @009 #19: addcy(sF,1)
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38001 // @00a #20: returni(enable)
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@3ff // #23: address(1023)
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// @3ff #24: [irq]
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34009 // @3ff #25: jump(isr)
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