2015-12-14 21:13:15 +03:00
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//--------------------------------------------------------------------------------
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// ClkDivider.v
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// Konstantin Pavlov, pavlovconst@gmail.com
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//--------------------------------------------------------------------------------
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// INFO --------------------------------------------------------------------------------
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// <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>.
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// <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>.
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2016-01-01 22:39:14 +03:00
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/*ClkDivider CD1 (
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.clk(),
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.nrst(),
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.out()
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);
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defparam CD1.WIDTH = 32;*/
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2015-12-14 21:13:15 +03:00
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module ClkDivider(clk,nrst,out);
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input wire clk;
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input wire nrst;
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output reg [(WIDTH-1):0] out = 0;
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parameter WIDTH = 32;
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always @ (posedge clk) begin
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if (~nrst) begin
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2016-03-23 21:18:08 +03:00
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out[(WIDTH-1):0] <= 0;
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2015-12-14 21:13:15 +03:00
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end
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else begin
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2016-03-23 21:18:08 +03:00
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out[(WIDTH-1):0] <= out[(WIDTH-1):0] + 1'b1;
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2015-12-14 21:13:15 +03:00
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end
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end
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endmodule
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