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42 lines
1.0 KiB
Coq
42 lines
1.0 KiB
Coq
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//--------------------------------------------------------------------------------
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// StaticDelay.v
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// Konstantin Pavlov, pavlovconst@gmail.com
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//--------------------------------------------------------------------------------
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// INFO --------------------------------------------------------------------------------
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// <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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//
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/*StaticDelay SD1 (
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.clk(),
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.in(),
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.out()
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);
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defparam SD1.LENGTH = 2;
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defparam SD1.WIDTH = 1;*/
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module StaticDelay(clk, in, out);
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// there is no reset on purpose of inferring Xilinx`s SRL16E primitive
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input wire clk;
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input wire [(WIDTH-1):0] in;
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output wire [(WIDTH-1):0] out;
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parameter LENGTH = 2; // length of each delay chain
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parameter WIDTH = 1; // independent channels
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//(* keep = "true" *)
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reg [(LENGTH*WIDTH-1):0] data = 0;
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always @ (posedge clk) begin
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data[(LENGTH*WIDTH-1):0] <= data[(LENGTH*WIDTH-1):0] << WIDTH;
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data[(WIDTH-1):0] <= in[(WIDTH-1):0];
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end
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assign
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out[(WIDTH-1):0] = data[(LENGTH*WIDTH-1):((LENGTH-1)*WIDTH)];
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endmodule
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