mirror of
https://github.com/pConst/basic_verilog.git
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44 lines
1.1 KiB
Coq
44 lines
1.1 KiB
Coq
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//--------------------------------------------------------------------------------
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// EdgeDetect.v
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// Konstantin Pavlov, pavlovconst@gmail.com
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//--------------------------------------------------------------------------------
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// INFO --------------------------------------------------------------------------------
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// <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>.
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// <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>, <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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// <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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module EdgeDetect(clk, nrst, rising, falling, in, out);
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input wire clk;
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input wire nrst;
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input wire [(WIDTH-1):0] in;
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output reg [(WIDTH-1):0] rising = 0;
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output reg [(WIDTH-1):0] falling = 0;
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output wire [(WIDTH-1):0] out;
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parameter WIDTH = 1;
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reg [(WIDTH-1):0] in_prev = 0;
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always @ (posedge clk) begin
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if (~nrst) begin
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in_prev <= 0;
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rising <= 0;
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falling <= 0;
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end
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else begin
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in_prev <= in;
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rising[(WIDTH-1):0] <= in[(WIDTH-1):0] & ~in_prev[(WIDTH-1):0];
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falling[(WIDTH-1):0] <= ~in[(WIDTH-1):0] & in_prev[(WIDTH-1):0];
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end
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end
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assign
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out[(WIDTH-1):0] = rising[(WIDTH-1):0] | falling[(WIDTH-1):0];
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endmodule
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