basic_verilog/Advanced Synthesis Cookbook/storage/mlab_delay_tb.sv

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`timescale 1 ps / 1 ps
module mlab_delay_tb ();
	
parameter BITS_PER_WORD = 9;
parameter WORDS = 46;

reg clk = 0;
reg [WORDS * BITS_PER_WORD - 1 : 0] din = 0;
wire [WORDS * BITS_PER_WORD - 1 : 0]  dout;
reg ena = 1'b1;
wire parity_error;

mlab_delay dut (.*);
defparam dut .WORDS = WORDS;
defparam dut .BITS_PER_WORD = BITS_PER_WORD;
defparam dut .LATENCY = 10;

always @(posedge clk) begin
	if (ena) din <= din + 1'b1;
end

always @(negedge clk) ena = $random();

reg [WORDS * BITS_PER_WORD - 1 : 0] delta;
always @(posedge clk) delta <= din - dout;

always begin
	#5 clk = ~clk;
end

reg fail = 0;
always @(posedge clk) begin
	if (!parity_error && delta != 10) fail = 1'b1;
end

initial begin
	#10
	@(negedge parity_error);
	#100000
	if (!fail) $display ("PASS");
	$stop();
end

endmodule