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48 lines
2.0 KiB
Coq
48 lines
2.0 KiB
Coq
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// Copyright 2008 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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// This is an interesting circut that effectively moves a clock
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// off of the global clock network onto local routing. It
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// will cause some skew and duty distortion. In the strict
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// sense you can use this circuit to avoid gated clock warnings.
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// However, it is unclear that the underlying timing situation is
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// any better than the simple "out = clk" version.
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module clock_follow (
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input clk_in,
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output clk_out
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);
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reg rp = 1'b0;
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reg rn = 1'b0;
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always @(posedge clk_in) begin
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rp <= ~rp;
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end
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always @(negedge clk_in) begin
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rn <= ~rp;
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end
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assign clk_out = ~rp ^ rn;
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endmodule
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