mirror of
https://github.com/pConst/basic_verilog.git
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85 lines
2.5 KiB
Coq
85 lines
2.5 KiB
Coq
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// Copyright 2007 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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module fourbyfour_sad_tb ();
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wire [7:0] x0,x1,x2,x3,x4,x5,x6,x7,x8,x9,xa,xb,xc,xd,xe,xf;
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wire [7:0] y0,y1,y2,y3,y4,y5,y6,y7,y8,y9,ya,yb,yc,yd,ye,yf;
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reg [8*16*2-1:0] data;
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reg fail;
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assign {x0,x1,x2,x3,x4,x5,x6,x7,x8,x9,xa,xb,xc,xd,xe,xf,
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y0,y1,y2,y3,y4,y5,y6,y7,y8,y9,ya,yb,yc,yd,ye,yf} = data;
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wire [11:0] sad;
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fourbyfour_sad fs (
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x0,x1,x2,x3,x4,x5,x6,x7,x8,x9,xa,xb,xc,xd,xe,xf,
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y0,y1,y2,y3,y4,y5,y6,y7,y8,y9,ya,yb,yc,yd,ye,yf,
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sad
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);
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// compute correct answer using entirely different method
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wire [12:0] diff[15:0];
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genvar i;
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generate
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for (i = 0; i<16; i = i+1)
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begin : check
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wire [12:0] j,k;
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assign j = data[i*8+7:i*8];
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assign k = data[8*16+i*8+7:8*16+i*8];
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assign diff[i] = (j > k) ? j - k : k - j;
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end
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endgenerate
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integer q, cume;
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always begin
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#100 cume = 0;
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for (q = 0; q<16; q=q+1)
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begin : sum
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cume = cume + diff[q];
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end
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end
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initial begin
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data = 0;
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fail = 0;
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#1000000
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if (!fail) $display ("PASS");
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$stop;
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end
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// stim generate and check
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always begin
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#1000 data = {$random,$random,$random,$random,
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$random,$random,$random,$random};
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#1000 if (cume != sad) begin
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$display ("Mismatch at time %d",$time);
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fail = 1;
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end
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end
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endmodule
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