basic_verilog/Advanced Synthesis Cookbook/counter/system_timer_tb.v

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//
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module system_timer_tb ();

reg clk = 0, rst = 0;
wire usecond_pulse;
wire msecond_pulse;
wire second_pulse;


wire [9:0] usecond_cntr;
wire [9:0] msecond_cntr;
wire [5:0] second_cntr;
wire [5:0] minute_cntr;
wire [4:0] hour_cntr;
wire [9:0] day_cntr;

system_timer dut (
	.clk,
	.rst,
	
	.usecond_cntr,
	.msecond_cntr,
	.second_cntr,
	.minute_cntr,
	.hour_cntr,
	.day_cntr,
		
	.usecond_pulse,
	.msecond_pulse,
	.second_pulse
);
	defparam dut .CLOCK_MHZ = 100;

always begin
	#5 clk = ~clk;
end

initial begin
	@(negedge clk);
	rst = 1;
	@(negedge clk);
	rst = 0;	
	#10000100

	// cursory activity check, better tested in hardware
	if (usecond_cntr == 10'h0 &&
		msecond_cntr == 10'ha) $display ("PASS");
	$stop();
end

endmodule