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51 lines
2.2 KiB
Coq
51 lines
2.2 KiB
Coq
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// Copyright 2008 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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// baeckler - 09-16-2008
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// this is essentially a 64 to 7 compressor. The first two
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// layers are LUT based.
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//
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module sum_of_64 (
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input [63:0] data,
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output [6:0] sum
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);
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// first and second layers - LUT based
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wire [3:0] sum_a,sum_b,sum_c,sum_d,sum_e;
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wire [2:0] sum_f;
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twelve_four_comp ca (.data(data[11:0]),.sum(sum_a));
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twelve_four_comp cb (.data(data[23:12]),.sum(sum_b));
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twelve_four_comp cc (.data(data[35:24]),.sum(sum_c));
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twelve_four_comp cd (.data(data[47:36]),.sum(sum_d));
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twelve_four_comp ce (.data(data[59:48]),.sum(sum_e));
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six_three_comp cf (.data({2'b0,data[63:60]}),.sum(sum_f));
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// third layer binary adders
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wire[4:0] sum_g = sum_a + sum_b;
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wire[4:0] sum_h = sum_c + sum_d;
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wire[4:0] sum_i = sum_e + sum_f;
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// fourth layer ternary add
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ternary_add ta (.a(sum_g),.b(sum_h),.c(sum_i),.o(sum));
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defparam ta .WIDTH=5;
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endmodule
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