mirror of
https://github.com/pConst/basic_verilog.git
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84 lines
2.9 KiB
Coq
84 lines
2.9 KiB
Coq
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// Copyright 2009 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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// baeckler - 03-23-2009
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// simple clock crossing with ready / valid signals
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module clock_crossing_fifo #(
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parameter DAT_WIDTH = 16,
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parameter WORDS = 32
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)
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(
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input wrclk,
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input wdata_valid,
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input [DAT_WIDTH-1:0] wdata,
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output wdata_ready,
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input rdclk,
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input rdata_ready,
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output [DAT_WIDTH-1:0] rdata,
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output reg rdata_valid
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);
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`include "log2.inc"
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wire wrreq, rdreq, rdempty, wrfull;
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assign wdata_ready = !wrfull;
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assign wrreq = wdata_valid & wdata_ready;
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assign rdreq = !rdempty & (!rdata_valid | rdata_ready);
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initial rdata_valid = 1'b0;
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always @(posedge rdclk) begin
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if (rdata_ready) rdata_valid <= 1'b0;
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if (rdreq) rdata_valid <= 1'b1;
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end
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dcfifo dcfifo_component (
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.wrclk (wrclk),
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.rdreq (rdreq),
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.rdclk (rdclk),
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.wrreq (wrreq),
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.data (wdata),
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.rdempty (rdempty),
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.wrfull (wrfull),
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.q (rdata),
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.aclr (1'b0),
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.rdfull (),
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.rdusedw (),
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.wrempty (),
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.wrusedw ()
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);
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defparam
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dcfifo_component.intended_device_family = "Stratix II",
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dcfifo_component.lpm_numwords = WORDS,
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dcfifo_component.lpm_showahead = "OFF",
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dcfifo_component.lpm_type = "dcfifo",
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dcfifo_component.lpm_width = DAT_WIDTH,
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dcfifo_component.lpm_widthu = log2(WORDS-1),
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dcfifo_component.overflow_checking = "ON",
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dcfifo_component.rdsync_delaypipe = 4,
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dcfifo_component.underflow_checking = "ON",
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dcfifo_component.use_eab = "ON",
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dcfifo_component.wrsync_delaypipe = 4;
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endmodule
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