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27 lines
760 B
Tcl
27 lines
760 B
Tcl
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#------------------------------------------------------------------------------
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# published as part of https://github.com/pConst/basic_verilog
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# Konstantin Pavlov, pavlovconst@gmail.com
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#------------------------------------------------------------------------------
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# Create a project
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open_project proj -reset
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add_files hls_operator.cpp
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add_files -tb hls_operator_tb.cpp
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set_top hls_operator
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# Create a solution
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open_solution -reset sol1 -flow_target vitis
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set_part {xcvu9p-flga2104-2-i}
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create_clock -period 5 -name default
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#csim_design
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csynth_design
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#cosim_design
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#export_design -rtl verilog -format ip_catalog -output /home/kp/tmp
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#export_design -flow syn -rtl verilog -format ip_catalog
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#export_design -flow impl -rtl verilog -format ip_catalog
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exit
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