basic_verilog/Advanced Synthesis Cookbook/counter/cntr.v

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// baeckler - 06-16-2006
//
// Standard issue binary counter with all of the register secondary
// hardware. (1 cell per bit)

module cntr (clk,ena,rst,sload,sdata,sclear,q);

parameter WIDTH = 16;

input clk,ena,rst,sload,sclear;
input [WIDTH-1:0] sdata;

output [WIDTH-1:0] q;
reg [WIDTH-1:0] q;

always @(posedge clk or posedge rst) begin
	if (rst) q <= 0;
	else begin
		if (ena) begin
			if (sclear) q <= 0;
			else if (sload) q <= sdata;
			else q <= q + 1'b1;
		end
	end
end

endmodule