basic_verilog/Advanced Synthesis Cookbook/interlaken_lane/scrambler_lfsr.v

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`timescale 1 ps / 1 ps

// baeckler - 09-17-2008

// 58 bit loadable LFSR - x^58 + x^39 + 1
// with 64 bit output for use as a scrambler

module scrambler_lfsr (
	input clk, arst,
	input verify,		
	input load,
	input [57:0] load_d,
	input evolve,
	output [63:0] q,
	output verify_fail,
	output verify_pass		   
);

// the RESET_VAL must be non-zero and 
// for noise should be unique per TX lane
parameter RESET_VAL = 58'h1234567_89abcdef;

reg [57:0] lfsr;
wire [63:0] next;

assign q = {lfsr[57:0], next[63:58]};

// This is from the Interlaken scrambler sample
// Verilog, regrouped to words.
assign next = {lfsr,lfsr[57:52]} ^ 
			{lfsr[38:0],lfsr[38:14]} ^ 
			{39'b0,lfsr[57:39],6'b0};
  
always @(posedge clk or posedge arst) begin
	if(arst) begin
		lfsr <= RESET_VAL; 
	end else begin
		if (load) lfsr <= load_d;
		else if (evolve) lfsr <= next[57:0];
	end
end	

reg last_verify, match;
always @(posedge clk or posedge arst) begin
	if(arst) begin
		last_verify <= 1'b0;
		match <= 1'b0; 
	end
	else begin
		last_verify <= verify;
		match <= (lfsr == load_d);
	end
end

assign verify_fail = last_verify & !match;
assign verify_pass = last_verify & match;

endmodule