basic_verilog/Advanced Synthesis Cookbook/interlaken_lane/twelve_four_comp.v

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`timescale 1 ps / 1 ps

// baeckler -09-15-2008
// This is intended to use exactly ten LUTs in two levels.

module twelve_four_comp (data,sum);

input [11:0] data;
output [3:0] sum;

wire [3:0] sum /* synthesis keep */;
wire [2:0] sum_a,sum_b;

six_three_comp ca (.data(data[5:0]),.sum(sum_a));
six_three_comp cb (.data(data[11:6]),.sum(sum_b));
sum_of_3bit_pair st (.a(sum_a),.b(sum_b),.sum(sum));

endmodule