basic_verilog/Advanced Synthesis Cookbook/storage/gray_to_bin.v

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`timescale 1 ps / 1 ps

// output bits are an XOR function of more significant bits, the
// area required may increase somewhat irregularly with WIDTH
// as the synthesis tool selects different area / depth tradeoffs

module gray_to_bin (gray,bin);

parameter WIDTH = 8;

input [WIDTH-1:0] gray;
output [WIDTH-1:0] bin;
wire [WIDTH-1:0] bin;

assign bin[WIDTH-1] = gray[WIDTH-1];
genvar i;
generate
for (i=WIDTH-2; i>=0; i=i-1)
  begin: gry_to_bin
    assign bin[i] = bin[i+1] ^ gray[i];
  end
endgenerate

endmodule