basic_verilog/Advanced Synthesis Cookbook/random/word_stream_scramble_tb.v

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module word_stream_scramble_tb ();

reg clk,rst,ena;
reg [7:0] din;
wire [7:0] sc_dout, dout;
wire sc_dout_valid, dout_valid;

word_stream_scramble ws (
	.clk(clk),
	.ena(rst | ena),
	.rst(rst),
	.din(din),
	.dout(sc_dout),
	.dout_valid(sc_dout_valid)
);
defparam ws .WORD_LEN = 8;

word_stream_scramble uws (
	.clk(clk),
	.ena(rst | sc_dout_valid),
	.rst(rst),
	.din(sc_dout),
	.dout(dout),
	.dout_valid(dout_valid)
);
defparam uws .WORD_LEN = 8;
defparam uws .SCRAMBLE = 1'b0;

reg fail;

initial begin
	clk = 0;
	rst = 0;
	din = 0;
	ena = 1;
	fail = 0;
	#10 
	rst = 1'b1;
	@(posedge clk);
	@(negedge clk);
	rst = 1'b0;
	
	#1000000 if (!fail) $display ("PASS");
	$stop();
end

reg [7:0] expect_out;
always @(posedge clk) begin
	if (rst) begin
		din <= 0;
		expect_out <= 0;
	end
	else begin
		din <= din + 1'b1;
		if (dout_valid) expect_out <= expect_out + 1'b1;
	end
end

always @(posedge clk) begin
	#5 if (expect_out !== dout) begin
		$display ("Mismatch at time %d",$time);
		fail = 1;
	end
end

always begin
	#100 clk <= ~clk;
end

endmodule