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https://github.com/pConst/basic_verilog.git
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50 lines
1.2 KiB
Plaintext
50 lines
1.2 KiB
Plaintext
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/* Symbol Table */
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// here = LABEL: 17
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// int = LABEL: 1023
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// isr = LABEL: 18
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// s0 = REGISTER: 0
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// s1 = REGISTER: 1
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// s2 = REGISTER: 2
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// s3 = REGISTER: 3
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// s4 = REGISTER: 4
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// s5 = REGISTER: 5
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// s6 = REGISTER: 6
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// s7 = REGISTER: 7
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// s8 = REGISTER: 8
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// s9 = REGISTER: 9
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// sA = REGISTER: 10
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// sB = REGISTER: 11
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// sC = REGISTER: 12
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// sD = REGISTER: 13
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// sE = REGISTER: 14
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// sF = REGISTER: 15
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// start = LABEL: 0
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/* Program Code */
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// #1: ; test3m.psm
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// @000 #3: [start]
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000ca // @000 #4: load(s0,202)
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001fe // @001 #5: load(s1,254)
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3f010 // @002 #6: mul(s0,s1)
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2c101 // @003 #8: output(s1,1)
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2c000 // @004 #9: output(s0,0)
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000de // @005 #11: load(s0,222)
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002ad // @006 #12: load(s2,173)
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3f020 // @007 #13: mul(s0,s2)
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2c103 // @008 #15: output(s1,3)
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2c002 // @009 #16: output(s0,2)
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001ca // @00a #18: load(s1,202)
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000fe // @00b #19: load(s0,254)
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003be // @00c #21: load(s3,190)
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002ef // @00d #22: load(s2,239)
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23200 // @00e #24: addw(s2,s0)
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2c305 // @00f #26: output(s3,5)
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2c204 // @010 #27: output(s2,4)
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// @011 #29: [here]
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34011 // @011 #30: jump(here)
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// @012 #32: [isr]
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34012 // @012 #33: jump(isr)
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// @013 #35: [int]
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@3ff // #35: address(1023)
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34012 // @3ff #36: jump(isr)
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