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https://github.com/pConst/basic_verilog.git
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26 lines
214 B
Plaintext
26 lines
214 B
Plaintext
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address $0
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start:
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load s0, 0
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load sE, 0
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load sF, 0
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interrupt enable
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loop:
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addcy s0, $f0
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call nc, func
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jump loop
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func:
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add sE, 3
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return
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isr:
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addcy sF, 1
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returni enable
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address $3ff
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irq:
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jump isr
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