mirror of
https://github.com/pConst/basic_verilog.git
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36 lines
1.0 KiB
Coq
36 lines
1.0 KiB
Coq
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//--------------------------------------------------------------------------------
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// DeBounce.v
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// Konstantin Pavlov, pavlovconst@gmail.com
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//--------------------------------------------------------------------------------
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// INFO --------------------------------------------------------------------------------
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// <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> (<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>) <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>.
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// <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD> <EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD> (<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>) <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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module DeBounce(clk,nrst,in,out);
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input wire clk;
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input wire nrst;
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input wire [(WIDTH-1):0] in;
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output wire [(WIDTH-1):0] out; // also "present state"
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parameter WIDTH = 1;
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reg [(WIDTH-1):0] prev = 0;
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always @ (posedge clk) begin
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if (~nrst) begin
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prev <= 0;
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end
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else begin
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prev[(WIDTH-1):0] <= in[(WIDTH-1):0];
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end
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end
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wire [(WIDTH-1):0] switch_hi = (prev[(WIDTH-1):0] & in[(WIDTH-1):0]);
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wire [(WIDTH-1):0] n_switch_lo = (prev[(WIDTH-1):0] | in[(WIDTH-1):0]);
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SetReset SR(clk,nrst,switch_hi[(WIDTH-1):0],~n_switch_lo[(WIDTH-1):0],out[(WIDTH-1):0]);
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defparam SR.WIDTH = WIDTH;
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endmodule
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