mirror of
https://github.com/pConst/basic_verilog.git
synced 2025-01-28 07:02:55 +08:00
248 lines
12 KiB
Coq
248 lines
12 KiB
Coq
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// Copyright 2008 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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//
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// 24 bit CRC of 64 data bits (reversed - MSB first)
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// polynomial : 00328b63
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// x^21 + x^20 + x^17 + x^15 + x^11 + x^9 + x^8 + x^6 + x^5 + x^1 + x^0
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//
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// CCCCCCCCCCCCCCCCCCCCCCCC DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD
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// 000000000011111111112222 0000000000111111111122222222223333333333444444444455555555556666
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// 012345678901234567890123 0123456789012345678901234567890123456789012345678901234567890123
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// C00 = ........................ #..##.###.##..#.#......#.....####.#.####.#....#.##..##..#.###.##
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// C01 = ........................ ##.#.##..##.#.####.....##....#...####...###...###.#.#.#.###..##.
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// C02 = ........................ .##.#.##..##.#.####.....##....#...####...###...###.#.#.#.###..##
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// C03 = ........................ ..##.#.##..##.#.####.....##....#...####...###...###.#.#.#.###..#
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// C04 = ........................ ...##.#.##..##.#.####.....##....#...####...###...###.#.#.#.###..
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// C05 = ........................ #..#.##.##.#.#....####.#...########.#...##..##..####.##....#.#.#
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// C06 = ........................ ##.#....##.##...#..######...#....#.##.##..#..#..#.##.####.##...#
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// C07 = ........................ .##.#....##.##...#..######...#....#.##.##..#..#..#.##.####.##...
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// C08 = ........................ #.#.#####....#..#.#..##.###..#.##.###..##...#.#####....#.#.#.###
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// C09 = ........................ ##..##...###....##.#..#..###.#.#.###..###....###..####.....#....
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// C10 = ........................ .##..##...###....##.#..#..###.#.#.###..###....###..####.....#...
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// C11 = ........................ #.#.#...#.#.###.#.##.#.##..##.#.####..###.#...##......###.######
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// C12 = ........................ .#.#.#...#.#.###.#.##.#.##..##.#.####..###.#...##......###.#####
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// C13 = ........................ ..#.#.#...#.#.###.#.##.#.##..##.#.####..###.#...##......###.####
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// C14 = ........................ ...#.#.#...#.#.###.#.##.#.##..##.#.####..###.#...##......###.###
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// C15 = ........................ #..#...#..###....##.#.#..#.####..........####...######..#.......
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// C16 = ........................ .#..#...#..###....##.#.#..#.####..........####...######..#......
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// C17 = ........................ #.############..#..##.###..#......#.####.#.###..####..###..##.##
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// C18 = ........................ .#.############..#..##.###..#......#.####.#.###..####..###..##.#
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// C19 = ........................ ..#.############..#..##.###..#......#.####.#.###..####..###..##.
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// C20 = ........................ #...##...#..##.#...#..#..###.#.##.#.#.#.#.#.#..#.#.#..#.##..#...
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// C21 = ........................ ##.###.##..#.#......#.....####.#.####.#....#.##..##..#.###.#####
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// C22 = ........................ .##.###.##..#.#......#.....####.#.####.#....#.##..##..#.###.####
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// C23 = ........................ ..##.###.##..#.#......#.....####.#.####.#....#.##..##..#.###.###
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//
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// Number of XORs used is 24
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// Maximum XOR input count is 40
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// Best possible depth in 4 LUTs = 3
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// Best possible depth in 5 LUTs = 3
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// Best possible depth in 6 LUTs = 3
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// Total XOR inputs 788
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//
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// Special signal relations -
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// none
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//
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module crc24_dat64_only_flat (d,crc_out);
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input[63:0] d;
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output[23:0] crc_out;
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wire[23:0] crc_out;
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assign crc_out[0] =
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d[63] ^ d[62] ^ d[60] ^ d[59] ^ d[58] ^ d[56] ^
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d[53] ^ d[52] ^ d[49] ^ d[48] ^ d[46] ^ d[41] ^ d[39] ^
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d[38] ^ d[37] ^ d[36] ^ d[34] ^ d[32] ^ d[31] ^ d[30] ^
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d[29] ^ d[23] ^ d[16] ^ d[14] ^ d[11] ^ d[10] ^ d[8] ^
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d[7] ^ d[6] ^ d[4] ^ d[3] ^ d[0];
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assign crc_out[1] =
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d[62] ^ d[61] ^ d[58] ^ d[57] ^ d[56] ^ d[54] ^
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d[52] ^ d[50] ^ d[48] ^ d[47] ^ d[46] ^ d[42] ^ d[41] ^
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d[40] ^ d[36] ^ d[35] ^ d[34] ^ d[33] ^ d[29] ^ d[24] ^
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d[23] ^ d[17] ^ d[16] ^ d[15] ^ d[14] ^ d[12] ^ d[10] ^
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d[9] ^ d[6] ^ d[5] ^ d[3] ^ d[1] ^ d[0];
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assign crc_out[2] =
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d[63] ^ d[62] ^ d[59] ^ d[58] ^ d[57] ^ d[55] ^
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d[53] ^ d[51] ^ d[49] ^ d[48] ^ d[47] ^ d[43] ^ d[42] ^
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d[41] ^ d[37] ^ d[36] ^ d[35] ^ d[34] ^ d[30] ^ d[25] ^
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d[24] ^ d[18] ^ d[17] ^ d[16] ^ d[15] ^ d[13] ^ d[11] ^
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d[10] ^ d[7] ^ d[6] ^ d[4] ^ d[2] ^ d[1];
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assign crc_out[3] =
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d[63] ^ d[60] ^ d[59] ^ d[58] ^ d[56] ^ d[54] ^
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d[52] ^ d[50] ^ d[49] ^ d[48] ^ d[44] ^ d[43] ^ d[42] ^
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d[38] ^ d[37] ^ d[36] ^ d[35] ^ d[31] ^ d[26] ^ d[25] ^
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d[19] ^ d[18] ^ d[17] ^ d[16] ^ d[14] ^ d[12] ^ d[11] ^
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d[8] ^ d[7] ^ d[5] ^ d[3] ^ d[2];
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assign crc_out[4] =
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d[61] ^ d[60] ^ d[59] ^ d[57] ^ d[55] ^ d[53] ^
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d[51] ^ d[50] ^ d[49] ^ d[45] ^ d[44] ^ d[43] ^ d[39] ^
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d[38] ^ d[37] ^ d[36] ^ d[32] ^ d[27] ^ d[26] ^ d[20] ^
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d[19] ^ d[18] ^ d[17] ^ d[15] ^ d[13] ^ d[12] ^ d[9] ^
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d[8] ^ d[6] ^ d[4] ^ d[3];
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assign crc_out[5] =
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d[63] ^ d[61] ^ d[59] ^ d[54] ^ d[53] ^ d[51] ^
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d[50] ^ d[49] ^ d[48] ^ d[45] ^ d[44] ^ d[41] ^ d[40] ^
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d[36] ^ d[34] ^ d[33] ^ d[32] ^ d[31] ^ d[30] ^ d[29] ^
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d[28] ^ d[27] ^ d[23] ^ d[21] ^ d[20] ^ d[19] ^ d[18] ^
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d[13] ^ d[11] ^ d[9] ^ d[8] ^ d[6] ^ d[5] ^ d[3] ^
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d[0];
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assign crc_out[6] =
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d[63] ^ d[59] ^ d[58] ^ d[56] ^ d[55] ^ d[54] ^
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d[53] ^ d[51] ^ d[50] ^ d[48] ^ d[45] ^ d[42] ^ d[39] ^
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d[38] ^ d[36] ^ d[35] ^ d[33] ^ d[28] ^ d[24] ^ d[23] ^
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d[22] ^ d[21] ^ d[20] ^ d[19] ^ d[16] ^ d[12] ^ d[11] ^
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d[9] ^ d[8] ^ d[3] ^ d[1] ^ d[0];
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assign crc_out[7] =
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d[60] ^ d[59] ^ d[57] ^ d[56] ^ d[55] ^ d[54] ^
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d[52] ^ d[51] ^ d[49] ^ d[46] ^ d[43] ^ d[40] ^ d[39] ^
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d[37] ^ d[36] ^ d[34] ^ d[29] ^ d[25] ^ d[24] ^ d[23] ^
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d[22] ^ d[21] ^ d[20] ^ d[17] ^ d[13] ^ d[12] ^ d[10] ^
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d[9] ^ d[4] ^ d[2] ^ d[1];
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assign crc_out[8] =
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d[63] ^ d[62] ^ d[61] ^ d[59] ^ d[57] ^ d[55] ^
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d[50] ^ d[49] ^ d[48] ^ d[47] ^ d[46] ^ d[44] ^ d[40] ^
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d[39] ^ d[36] ^ d[35] ^ d[34] ^ d[32] ^ d[31] ^ d[29] ^
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d[26] ^ d[25] ^ d[24] ^ d[22] ^ d[21] ^ d[18] ^ d[16] ^
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d[13] ^ d[8] ^ d[7] ^ d[6] ^ d[5] ^ d[4] ^ d[2] ^
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d[0];
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assign crc_out[9] =
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d[59] ^ d[53] ^ d[52] ^ d[51] ^ d[50] ^ d[47] ^
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d[46] ^ d[45] ^ d[40] ^ d[39] ^ d[38] ^ d[35] ^ d[34] ^
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d[33] ^ d[31] ^ d[29] ^ d[27] ^ d[26] ^ d[25] ^ d[22] ^
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d[19] ^ d[17] ^ d[16] ^ d[11] ^ d[10] ^ d[9] ^ d[5] ^
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d[4] ^ d[1] ^ d[0];
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assign crc_out[10] =
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d[60] ^ d[54] ^ d[53] ^ d[52] ^ d[51] ^ d[48] ^
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d[47] ^ d[46] ^ d[41] ^ d[40] ^ d[39] ^ d[36] ^ d[35] ^
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d[34] ^ d[32] ^ d[30] ^ d[28] ^ d[27] ^ d[26] ^ d[23] ^
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d[20] ^ d[18] ^ d[17] ^ d[12] ^ d[11] ^ d[10] ^ d[6] ^
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d[5] ^ d[2] ^ d[1];
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assign crc_out[11] =
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d[63] ^ d[62] ^ d[61] ^ d[60] ^ d[59] ^ d[58] ^
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d[56] ^ d[55] ^ d[54] ^ d[47] ^ d[46] ^ d[42] ^ d[40] ^
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d[39] ^ d[38] ^ d[35] ^ d[34] ^ d[33] ^ d[32] ^ d[30] ^
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d[28] ^ d[27] ^ d[24] ^ d[23] ^ d[21] ^ d[19] ^ d[18] ^
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d[16] ^ d[14] ^ d[13] ^ d[12] ^ d[10] ^ d[8] ^ d[4] ^
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d[2] ^ d[0];
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assign crc_out[12] =
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d[63] ^ d[62] ^ d[61] ^ d[60] ^ d[59] ^ d[57] ^
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d[56] ^ d[55] ^ d[48] ^ d[47] ^ d[43] ^ d[41] ^ d[40] ^
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d[39] ^ d[36] ^ d[35] ^ d[34] ^ d[33] ^ d[31] ^ d[29] ^
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d[28] ^ d[25] ^ d[24] ^ d[22] ^ d[20] ^ d[19] ^ d[17] ^
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d[15] ^ d[14] ^ d[13] ^ d[11] ^ d[9] ^ d[5] ^ d[3] ^
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d[1];
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assign crc_out[13] =
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d[63] ^ d[62] ^ d[61] ^ d[60] ^ d[58] ^ d[57] ^
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d[56] ^ d[49] ^ d[48] ^ d[44] ^ d[42] ^ d[41] ^ d[40] ^
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d[37] ^ d[36] ^ d[35] ^ d[34] ^ d[32] ^ d[30] ^ d[29] ^
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d[26] ^ d[25] ^ d[23] ^ d[21] ^ d[20] ^ d[18] ^ d[16] ^
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d[15] ^ d[14] ^ d[12] ^ d[10] ^ d[6] ^ d[4] ^ d[2];
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assign crc_out[14] =
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d[63] ^ d[62] ^ d[61] ^ d[59] ^ d[58] ^ d[57] ^
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d[50] ^ d[49] ^ d[45] ^ d[43] ^ d[42] ^ d[41] ^ d[38] ^
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d[37] ^ d[36] ^ d[35] ^ d[33] ^ d[31] ^ d[30] ^ d[27] ^
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d[26] ^ d[24] ^ d[22] ^ d[21] ^ d[19] ^ d[17] ^ d[16] ^
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d[15] ^ d[13] ^ d[11] ^ d[7] ^ d[5] ^ d[3];
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assign crc_out[15] =
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d[56] ^ d[53] ^ d[52] ^ d[51] ^ d[50] ^ d[49] ^
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d[48] ^ d[44] ^ d[43] ^ d[42] ^ d[41] ^ d[30] ^ d[29] ^
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d[28] ^ d[27] ^ d[25] ^ d[22] ^ d[20] ^ d[18] ^ d[17] ^
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d[12] ^ d[11] ^ d[10] ^ d[7] ^ d[3] ^ d[0];
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assign crc_out[16] =
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d[57] ^ d[54] ^ d[53] ^ d[52] ^ d[51] ^ d[50] ^
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d[49] ^ d[45] ^ d[44] ^ d[43] ^ d[42] ^ d[31] ^ d[30] ^
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d[29] ^ d[28] ^ d[26] ^ d[23] ^ d[21] ^ d[19] ^ d[18] ^
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d[13] ^ d[12] ^ d[11] ^ d[8] ^ d[4] ^ d[1];
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assign crc_out[17] =
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d[63] ^ d[62] ^ d[60] ^ d[59] ^ d[56] ^ d[55] ^
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d[54] ^ d[51] ^ d[50] ^ d[49] ^ d[48] ^ d[45] ^ d[44] ^
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d[43] ^ d[41] ^ d[39] ^ d[38] ^ d[37] ^ d[36] ^ d[34] ^
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d[27] ^ d[24] ^ d[23] ^ d[22] ^ d[20] ^ d[19] ^ d[16] ^
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d[13] ^ d[12] ^ d[11] ^ d[10] ^ d[9] ^ d[8] ^ d[7] ^
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d[6] ^ d[5] ^ d[4] ^ d[3] ^ d[2] ^ d[0];
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assign crc_out[18] =
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d[63] ^ d[61] ^ d[60] ^ d[57] ^ d[56] ^ d[55] ^
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d[52] ^ d[51] ^ d[50] ^ d[49] ^ d[46] ^ d[45] ^ d[44] ^
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d[42] ^ d[40] ^ d[39] ^ d[38] ^ d[37] ^ d[35] ^ d[28] ^
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d[25] ^ d[24] ^ d[23] ^ d[21] ^ d[20] ^ d[17] ^ d[14] ^
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d[13] ^ d[12] ^ d[11] ^ d[10] ^ d[9] ^ d[8] ^ d[7] ^
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d[6] ^ d[5] ^ d[4] ^ d[3] ^ d[1];
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assign crc_out[19] =
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d[62] ^ d[61] ^ d[58] ^ d[57] ^ d[56] ^ d[53] ^
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d[52] ^ d[51] ^ d[50] ^ d[47] ^ d[46] ^ d[45] ^ d[43] ^
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d[41] ^ d[40] ^ d[39] ^ d[38] ^ d[36] ^ d[29] ^ d[26] ^
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d[25] ^ d[24] ^ d[22] ^ d[21] ^ d[18] ^ d[15] ^ d[14] ^
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d[13] ^ d[12] ^ d[11] ^ d[10] ^ d[9] ^ d[8] ^ d[7] ^
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d[6] ^ d[5] ^ d[4] ^ d[2];
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assign crc_out[20] =
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d[60] ^ d[57] ^ d[56] ^ d[54] ^ d[51] ^ d[49] ^
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d[47] ^ d[44] ^ d[42] ^ d[40] ^ d[38] ^ d[36] ^ d[34] ^
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d[32] ^ d[31] ^ d[29] ^ d[27] ^ d[26] ^ d[25] ^ d[22] ^
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d[19] ^ d[15] ^ d[13] ^ d[12] ^ d[9] ^ d[5] ^ d[4] ^
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d[0];
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assign crc_out[21] =
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d[63] ^ d[62] ^ d[61] ^ d[60] ^ d[59] ^ d[57] ^
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||
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d[56] ^ d[55] ^ d[53] ^ d[50] ^ d[49] ^ d[46] ^ d[45] ^
|
||
|
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d[43] ^ d[38] ^ d[36] ^ d[35] ^ d[34] ^ d[33] ^ d[31] ^
|
||
|
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d[29] ^ d[28] ^ d[27] ^ d[26] ^ d[20] ^ d[13] ^ d[11] ^
|
||
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d[8] ^ d[7] ^ d[5] ^ d[4] ^ d[3] ^ d[1] ^ d[0];
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||
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assign crc_out[22] =
|
||
|
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d[63] ^ d[62] ^ d[61] ^ d[60] ^ d[58] ^ d[57] ^
|
||
|
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d[56] ^ d[54] ^ d[51] ^ d[50] ^ d[47] ^ d[46] ^ d[44] ^
|
||
|
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d[39] ^ d[37] ^ d[36] ^ d[35] ^ d[34] ^ d[32] ^ d[30] ^
|
||
|
|
d[29] ^ d[28] ^ d[27] ^ d[21] ^ d[14] ^ d[12] ^ d[9] ^
|
||
|
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d[8] ^ d[6] ^ d[5] ^ d[4] ^ d[2] ^ d[1];
|
||
|
|
|
||
|
|
assign crc_out[23] =
|
||
|
|
d[63] ^ d[62] ^ d[61] ^ d[59] ^ d[58] ^ d[57] ^
|
||
|
|
d[55] ^ d[52] ^ d[51] ^ d[48] ^ d[47] ^ d[45] ^ d[40] ^
|
||
|
|
d[38] ^ d[37] ^ d[36] ^ d[35] ^ d[33] ^ d[31] ^ d[30] ^
|
||
|
|
d[29] ^ d[28] ^ d[22] ^ d[15] ^ d[13] ^ d[10] ^ d[9] ^
|
||
|
|
d[7] ^ d[6] ^ d[5] ^ d[3] ^ d[2];
|
||
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|
||
|
|
endmodule
|
||
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