basic_verilog/Advanced Synthesis Cookbook/arithmetic/karatsuba_mult_tb.v

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module karatsuba_mult_tb ();

parameter IN_WIDTH = 32; // smaller width for testing.  64x64 nominal

reg clk = 0;

reg [IN_WIDTH-1:0] a,b;
wire [2*IN_WIDTH-1:0] o;

////////////////////////////////
// DUT
////////////////////////////////

karatsuba_mult km (
	.clk(clk),
	.a(a),
	.b(b),
	.o(o)
);
defparam km .IN_WIDTH = IN_WIDTH;

////////////////////////////////
// functional model
////////////////////////////////
parameter LATENCY = 6;
reg [LATENCY * 2*IN_WIDTH-1:0] m;
wire [2*IN_WIDTH-1:0] o2 = m[LATENCY*2*IN_WIDTH-1:(LATENCY-1)*2*IN_WIDTH];

always @(posedge clk) begin
	m <= (m << 2*IN_WIDTH) | (a * b);
end

////////////////////////////////
// test stimulus + check
////////////////////////////////

always @(negedge clk) begin
	a = $random;
	b = $random;
end

reg fail = 0;

integer cyc = 0;
always @(posedge clk) begin
	cyc <= cyc + 1'b1;
	#2 if ((o2 !== o) && (cyc > LATENCY)) begin
		$display ("Mismatch at time %d",$time);
		fail = 1;
	end
end

initial begin
	#1000000 if (!fail) $display ("PASS");
	$stop();
end

always begin
	#100 clk = ~clk;
end

endmodule