basic_verilog/Advanced Synthesis Cookbook/interlaken_lane/dec_67_64.v

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`timescale 1 ps / 1 ps

// baeckler - 09-16-2008
// 67 to 64 decoder 

module dec_67_64 (
	input clk, arst,
	input [66:0] din,
	input pn_reverse, 
	output [64:0] dout, // bit 64=1 indicates control word
	output framing_error
);

assign dout[63:0] = din[63:0] ^ {64{din[66]}}; // +/- data
assign dout[64] = din[65] ^ pn_reverse; // 1 for control words
assign framing_error = ~din[64] ^ din[65];

endmodule