basic_verilog/Advanced Synthesis Cookbook/random/bilbo_lfsr_tb.v

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module bilbo_lfsr_tb ();

parameter WIDTH = 16;

reg clk,rst,sin,fail;
wire sout;
wire [WIDTH-1:0] out;
reg [WIDTH-1:0] in;
reg [1:0] mode;

bilbo_lfsr b (.pin(in),.pout(out),.shift_in(sin),.shift_out(sout),
	.mode(mode),.clk(clk),.rst(rst));
defparam b.WIDTH = WIDTH;

initial begin
	fail = 0;
	clk = 0;
	rst = 0;
	sin = 0;
	in = 0;
	mode = 0;
		
	#10 rst = 1;
	#10 rst = 0;
end

always begin 
	#1000 clk = ~clk;
end

reg [WIDTH-1:0] last_out;

always @(negedge clk) begin
	in = $random;
	sin = $random;
	mode = $random;
	last_out = out;
end

// test the shifting and pass through modes
always @(posedge clk) begin
	#10 if (mode == 0) begin
		if (out != in) begin
			$display ("Mode 0 failure");
			fail = 1;
		end
	end
	else if (mode == 1) begin
		if (out != ((last_out << 1) | sin)) begin
			$display ("Mode 1 failure");
			fail = 1;
		end
	end

	// other modes verified in system
end

initial begin
	#1000000
	if (!fail) $display ("PASS (not fully covered)");
	$stop();
end

endmodule