2022-05-16 19:39:38 +03:00
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// readme for "benchmark_projects" directory
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// published as part of https://github.com/pConst/basic_verilog
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// Konstantin Pavlov, pavlovconst@gmail.com
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2022-05-16 19:21:43 +03:00
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The directory contains single reference System Verilog codebase, compiled consistently for multiple FPGA platforms and vendors.
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2022-05-16 19:29:41 +03:00
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Supported IDE projects include
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2022-05-16 19:21:43 +03:00
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* Xilinx ISE
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* Xilinx Vivado
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* Intel Quartus
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* Gowin IDE
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Currently working on
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* Microsemi Libero
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* Lattice iCEcube
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* Lattice FOSS toolchain
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See comparative compile time results in ./benchmark_results.txt
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