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38 lines
791 B
Systemverilog
38 lines
791 B
Systemverilog
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//------------------------------------------------------------------------------
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// gray2bin.sv
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// Konstantin Pavlov, pavlovconst@gmail.com
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//------------------------------------------------------------------------------
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// INFO ------------------------------------------------------------------------
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// Binary to gray code converter
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// Combinational design
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/* --- INSTANTIATION TEMPLATE BEGIN ---
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gray2bin #(
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.WIDTH( 32 )
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) GB1 (
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.gray_in( ),
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.bin_out( )
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);
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--- INSTANTIATION TEMPLATE END ---*/
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module gray2bin #( parameter
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WIDTH = 32
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)(
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input [WIDTH-1:0] gray_in,
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output [WIDTH-1:0] bin_out
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);
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genvar i;
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generate
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for( i=0; i<WIDTH; i++ ) begin
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assign bin_out[i] = ^gray_in[WIDTH-1:i];
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end
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endgenerate
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endmodule
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