FPGA/basic_verilog
1
0
Fork 0
mirror of https://github.com/pConst/basic_verilog.git synced 2025-01-14 06:42:54 +08:00
Code Issues Releases Wiki Activity

Fix typo

Browse Source
This commit is contained in:
Konstantin Pavlov 2023-05-23 11:12:22 +03:00
parent b81fda635d
commit 0475ea0398
3 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
debounce_v1.v
View File

@ -7,7 +7,7 @@
// INFO ------------------------------------------------------------------------
// Button debounce v1
//
// - sampling inputs using configurable divided clock (ithis is the
// - sampling inputs using configurable divided clock (this is the
// simplest form of low-pass filter)
// - switching output only when both samples have equal level
// (this gives some form of hysteresis in case we sample unstable data)

2
debounce_v2.sv
View File

@ -7,7 +7,7 @@
// INFO ------------------------------------------------------------------------
// Button debounce v2, SystemVerilog version
//
// - sampling inputs using configurable divided clock (ithis is the
// - sampling inputs using configurable divided clock (this is the
// simplest form of low-pass filter)
//
// - in contrast with debounce_v1.v this implementation is switching output only

2
debounce_v2.v
View File

@ -7,7 +7,7 @@
// INFO ------------------------------------------------------------------------
// Button debounce v2
//
// - sampling inputs using configurable divided clock (ithis is the
// - sampling inputs using configurable divided clock (this is the
// simplest form of low-pass filter)
//
// - in contrast with debounce_v1.v this implementation is switching output only