From 0475ea039849c4258f800fb556f62bcf2e91f401 Mon Sep 17 00:00:00 2001 From: Konstantin Pavlov Date: Tue, 23 May 2023 11:12:22 +0300 Subject: [PATCH] Fix typo --- debounce_v1.v | 2 +- debounce_v2.sv | 2 +- debounce_v2.v | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/debounce_v1.v b/debounce_v1.v index a76b8a1..efac2a3 100644 --- a/debounce_v1.v +++ b/debounce_v1.v @@ -7,7 +7,7 @@ // INFO ------------------------------------------------------------------------ // Button debounce v1 // -// - sampling inputs using configurable divided clock (ithis is the +// - sampling inputs using configurable divided clock (this is the // simplest form of low-pass filter) // - switching output only when both samples have equal level // (this gives some form of hysteresis in case we sample unstable data) diff --git a/debounce_v2.sv b/debounce_v2.sv index 807f4b5..183bd41 100644 --- a/debounce_v2.sv +++ b/debounce_v2.sv @@ -7,7 +7,7 @@ // INFO ------------------------------------------------------------------------ // Button debounce v2, SystemVerilog version // -// - sampling inputs using configurable divided clock (ithis is the +// - sampling inputs using configurable divided clock (this is the // simplest form of low-pass filter) // // - in contrast with debounce_v1.v this implementation is switching output only diff --git a/debounce_v2.v b/debounce_v2.v index 95b527d..7bd22ac 100644 --- a/debounce_v2.v +++ b/debounce_v2.v @@ -7,7 +7,7 @@ // INFO ------------------------------------------------------------------------ // Button debounce v2 // -// - sampling inputs using configurable divided clock (ithis is the +// - sampling inputs using configurable divided clock (this is the // simplest form of low-pass filter) // // - in contrast with debounce_v1.v this implementation is switching output only