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Fix typo
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@ -7,7 +7,7 @@
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// INFO ------------------------------------------------------------------------
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// INFO ------------------------------------------------------------------------
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// Button debounce v1
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// Button debounce v1
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//
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//
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// - sampling inputs using configurable divided clock (ithis is the
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// - sampling inputs using configurable divided clock (this is the
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// simplest form of low-pass filter)
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// simplest form of low-pass filter)
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// - switching output only when both samples have equal level
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// - switching output only when both samples have equal level
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// (this gives some form of hysteresis in case we sample unstable data)
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// (this gives some form of hysteresis in case we sample unstable data)
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@ -7,7 +7,7 @@
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// INFO ------------------------------------------------------------------------
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// INFO ------------------------------------------------------------------------
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// Button debounce v2, SystemVerilog version
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// Button debounce v2, SystemVerilog version
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//
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//
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// - sampling inputs using configurable divided clock (ithis is the
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// - sampling inputs using configurable divided clock (this is the
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// simplest form of low-pass filter)
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// simplest form of low-pass filter)
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//
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//
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// - in contrast with debounce_v1.v this implementation is switching output only
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// - in contrast with debounce_v1.v this implementation is switching output only
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@ -7,7 +7,7 @@
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// INFO ------------------------------------------------------------------------
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// INFO ------------------------------------------------------------------------
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// Button debounce v2
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// Button debounce v2
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//
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//
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// - sampling inputs using configurable divided clock (ithis is the
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// - sampling inputs using configurable divided clock (this is the
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// simplest form of low-pass filter)
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// simplest form of low-pass filter)
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//
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//
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// - in contrast with debounce_v1.v this implementation is switching output only
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// - in contrast with debounce_v1.v this implementation is switching output only
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