From 0a7385391abfa9f49eda8fa839e74f749272bbd9 Mon Sep 17 00:00:00 2001 From: Konstantin Pavlov Date: Wed, 17 May 2023 13:07:48 +0300 Subject: [PATCH] Added modelsim / questasim error code cat --- info/list_of_all_questa_error_codes.txt | 39412 ++++++++++++++++++++++ 1 file changed, 39412 insertions(+) create mode 100644 info/list_of_all_questa_error_codes.txt diff --git a/info/list_of_all_questa_error_codes.txt b/info/list_of_all_questa_error_codes.txt new file mode 100644 index 0000000..21fdff4 --- /dev/null +++ b/info/list_of_all_questa_error_codes.txt @@ -0,0 +1,39412 @@ +# list_of_all_questa_error_codes.txt +# published as part of https://github.com/pConst/basic_verilog +# Konstantin Pavlov, pavlovconst@gmail.com + + +common Message # 1: +There is no additional information for this message. + + +common Message # 2: +A call to the specified C library function failed. This message might be +followed by another message that gives more information about the problem. + + +common Message # 3: +The specified system call failed. This message might be followed +by another message that gives more information about the problem. + + +common Message # 4: +Not enough memory was available when a memory allocation was requested. +If this message was displayed during simulation, check for the following +conditions to determine where a large amount of memory allocation might +be occurring: + o Large signal or variable arrays in VHDL + o Large memories in Verilog + o Excessive memory use by textio + (readline or writeline not being called to deallocate lines) + o Excessive use of VHDL access types where memory is not being freed + o FLI or PLI code that is allocating a lot of memory + o Rescheduling of the same event(s) that causes event cancellation + without advancing time to the point of the cancelled events +You can use the simulator command "mti_kcmd memstats" at various +points during simulation to help determine when excessive memory +allocation occurs. +Things you can do that may be helpful: + o Use the memory locking feature on HP-UX or the memory sharing + feature on Solaris. + o Use the 64-bit version of QuestaSim. + o Increase the size of your swap space. + o Add memory to your machine. + o In the case of event cancellation, you can use the QuestaSim GUI + to step through your HDL code to see if the same statements are + being executed without time being advanced to the point where the + previously cancelled events would have occurred. Cancelled events + are not removed from the time queue until their scheduled time is + reached, thus the memory allocated for cancelled events is not + freed until that time. + + +common Message # 5: +This message occurs when an attempt is made to use an invalid pointer +or a previously deallocated pointer. +The most common cause of this problem is an incorrect use of TextIO +objects and functions. In the following example: + line_out2 := line_out1; + writeline( output1, line_out1 ); + writeline( output2, line_out2 ); +line_out1 and line_out2 are set to point to the same allocated memory. +The first writeline function deallocates the memory pointed to by +line_out1, thereby also deallocating the memory pointed to by line_out2. +The second writeline function then fails. To write the same output to +two files, use the following statement to copy the line: + line_out2 := new string'(line_out1.all); + + +common Message # 6: +Another process has placed a lock on this library. Either that process +is still ongoing, or it has terminated abnormally leaving a lockfile +that must be removed before continuing. + + +common Message # 7: +A problem occurred while trying to open the specified file in the +specified mode. Verify that the path exists and that you have the +correct permissions in the directory. Also, if any environment variables +were used in the original specification of the filename, make sure that +they are set to valid values. +If required, consider specifying Verilog source library directory with '-y ' +This message might be followed by another message that gives more +information about the problem. + + +common Message # 8: +A problem occurred while trying to read the specified file. +This message might be followed by another message that gives more +information about the problem. + + +common Message # 9: +A problem occurred while trying to write the specified file. Verify that +there is space left on the disk where the file is attempting to be written. +QuestaSim writes to /tmp, the current directory, and to the work directory. +Make sure that space is available in each of these locations. +This message might be followed by another message that gives more +information about the problem. + + +common Message # 10: +A problem occurred while trying to close the specified file. +This message might be followed by another message that gives more +information about the problem. + + +common Message # 11: +The specified design unit could not be found in the specified library. +Verify that the library exists and that the design unit has been +compiled into it. + + +common Message # 12: +The second design unit has changed (or something that it depends upon +has changed), requiring it to be recompiled. Since the first design +unit depends on the second one, the first design unit must be recompiled +after the second one has been recompiled. + +This error message can be suppressed or downgraded to a note or warning. + +common Message # 13: +The second design unit, upon which the first design unit depends, has +changed and has been recompiled; therefore, the first design unit must +be recompiled. + + +common Message # 14: +The ini file indicated by the specified environment variable could not +be found or opened; therefore, the default ini file is used. Verify that +the ini file path is specified correctly, that it exists, and that you +have read permission. This message might be followed by another message +that gives more information about the problem. + + +common Message # 15: +A logical library name must be mapped to a physical directory path in +order to avoid problems that can occur with a circular dependency or +with a mapping to a name that is both a logical name and a physical name. +[DOC: QuestaSim Command Reference - vmap command] + + +common Message # 16: +The 'others' clause in the specified ini file refers to that same ini +file. The 'others' clause should be changed to refer to another ini file +or it should be removed. + + +common Message # 17: +A chain of one or more 'others' clauses in ini files eventually refers +back to a file at the beginning of the chain. An example of this is: +the 'others' clause in modelsim.ini refers to a.ini whose 'others' +clause refers to b.ini whose 'others' clause refers back to +modelsim.ini. Fix the 'others' clauses so that they do not create a +circular dependency. + + +common Message # 18: +The path/file that is pointed to by MGC_LOCATION_MAP does not exist or +cannot be accessed. Verify that MGC_LOCATION_MAP is set correctly, that +it includes the name of the location map file, that the path and file +exist, and that you have the correct permissions for access. This message +might be followed by another message that gives more information about the +problem. + + +common Message # 19: +The specified library could not be accessed at the specified location. +Verify that the directories in the path exist and have the proper access +permissions and that the "_info" file (with proper access permissions) +exists. This message might be preceded or followed by another message +that gives more information about the problem. + +The vlib command creates a QuestaSim library. The vmap command creates +the map from a logical library name to the physical library (directory). +Use the vmap command without arguments to find out how all the libraries +are mapped. In the absence of a mapping, the library is searched for in +the current working directory. + +One way this problem can occur is if the mapping for the library in your +modelsim.ini file contains an environment variable that is not set +in your environment. + +This error message can be suppressed or downgraded to a note or warning. + +common Message # 20: +The specified access cannot be made to the specified file. Verify that +the file exists and that you have the correct permissions for accessing +it. This message might be followed by another message that gives more +information about the problem. + + +common Message # 21: +The value of the specified environment variable could not be found. +Verify that the environment variable is actually set. + + +common Message # 22: +A call to getcwd() failed. Verify that you have read permission at each +directory level in the path to your current working directory. If the +full pathname of your current working directory is longer than the +specified maximum path length, then contact at http://supportnet.mentor.com to report this error. + + +common Message # 23: +A call to chdir() failed for the specified path. Verify that the path +exists and that you have the correct permissions to access this +directory. This message might be followed by another message that gives +more information about the problem. + + +common Message # 24: +A call to getcwd() for the specified path failed. Verify that you have +read permission at each directory level in this path. If the full +pathname of this path is longer than the specified maximum path length, +then contact at http://supportnet.mentor.com to report this error. + + +common Message # 25: +The specified library does not contain an accessible _info file, +therefore it cannot be referenced as a QuestaSim library. Verify that +the library has been created with the vlib command and that you have +the correct permissions for accessing it. This message might be +followed by another message that gives more information about the problem. + + +common Message # 26: +A call to lseek() failed on the specified file. This message might be +followed by another message that gives more information about the problem. + + +common Message # 27: +A call to mmap() failed on the specified file. This message might be +followed by another message that gives more information about the problem. + + +common Message # 28: +A call to the specified function failed on the specified file. This +message might be followed by another message that gives more information +about the problem. + +Here are some things to check: +o Is another process writing to or deleting the file that you are + trying to read/write/create? +o Are you trying to create/write a file to a disk that is almost full? +o Are you experiencing a timeout due to accessing a file across a + network? +o Are you trying to create/write a very large file (around 2 Gig or + more)? If so, is your system configured for large file support? + + +common Message # 29: +A call to stat() failed on the specified file. Verify that the file +exists and that you have the correct access permission for all +directories in the path. This message might be followed by another +message that gives more information about the problem. + + +common Message # 30: +A lock file could not be created at the specified location because the +maximum number of files is already locked. + + +common Message # 31: +An unlink() on the specified file failed. This message might be followed +by another message that gives more information about the problem. + + +common Message # 32: +The specified design unit is not of the expected type. Verify that you +have specified the correct design unit name and that the design unit +is of an appropriate type for the operation that you are trying to +perform. + + +common Message # 33: +Under Windows, file names of the form aux, con, nul, prn, aux.*, con.*, +nul.*, and prn.* are reserved for use by the OS; therefore, a QuestaSim +library cannot be created with this type of name. + + +common Message # 34: +The specified library cannot be created because it already exists. + + +common Message # 35: +A problem occurred while trying to create the specified directory. +Verify that the path up to the new directory exists, that you have the +correct permissions along the full path, and that you have enough disk +space. This message might be followed by another message that gives more +information about the problem. + + +common Message # 36: +In order for sm_entity to access a SmartModel, the libsm entry and one +of the libswift entries in the [lmc] section of the specified project +file must be uncommented. +[DOC: QuestaSim User's Manual - Logic Modeling SmartModels chapter] + + +common Message # 37: +In order for hm_entity to access a hardware model, the libhm entry and +one of the libsfi entries in the [lmc] section of the specified project +file must be uncommented. +[DOC: QuestaSim User's Manual - Logic Modeling hardware models chapter] + + +common Message # 40: +Attempting to change the maximum name length for the contents of a +library is not permitted. Once a library has been created with +-dos/-short or with -unix/-long, this aspect of the library is +permanent. + + +common Message # 41: +There was a problem when trying to rename the specified path in the +specified mode. Make sure that the path exists and that you have the +correct permissions in the directory. This message might be followed +by another message that gives more information about the problem. + + +common Message # 42: +The indicated library exists, but the format of the library is not +supported by this version of QuestaSim. This was probably caused by +a more recent installation of QuestaSim being used to create a library +that is not backward-compatible with the version of QuestaSim currently +in use. + + +common Message # 43: +This feature is not supported in this version of the product. +It may require a separate license or a different version. + + +common Message # 44: +A problem occurred while trying to create the specified file. Verify +that the path exists and that you have the correct permissions in the +directory. Also, if any environment variables were used in the original +specification of the filename, make sure that they are set to valid +values. This message might be followed by another message that gives +more information about the problem. + + +common Message # 45: +All SystemC modules to be instantiated by HDL design units should be +exported using the SC_MODULE_EXPORT macro. + + +common Message # 46: +Either the port size is based on a generic value or the port type is not +supported at the SystemC-HDL boundary. Please refer to the User's Manual +for details on the supported port types. + + +common Message # 47: +vmake does not support SystemC modules. + + +common Message # 48: +Check your QuestaSim installation and make sure your path is set to +point to the correct location of QuestaSim. + + +common Message # 49: +vdel currently does not support deletion of individual SystemC design units. +Use vdel -allsystemc to delete all SystemC design unit in a given library. + + +common Message # 50: +QuestaSim uses the system() call to produce intermediate output. +The system() call has failed. Please check the logfile for further +information. + + +common Message # 51: +QuestaSim uses the system() call to produce intermediate output. +The system() call appears to have succeeded, but the expected output +file does not exist. Usually this means that the command that was +executed failed in some way, but did not return a non-zero exit status. +The following directories may be used to write temporary files. +Check if these directories have enough disk space: + o $TMPDIR + o P_tmpdir + o current working directory + + +common Message # 52: +An attempt to suppress a message or change its severity level failed +because the message number does not correspond to a message in the +message system. + + +common Message # 53: +An attempt to suppress an error message or change its severity level +failed because the error message is not suppressible/downgradable. +If the message needs to be suppressed/downgraded then please contact +http://supportnet.mentor.com to file an enhancement request. It may not +be possible to suppress some messages. + + +common Message # 54: +The total number of unnamed optimized designs that this library can hold +must be set to an integer value from 1 to 32000. + + +common Message # 55: +Please specify only one scalar type and one vector type. + + +common Message # 56: +The dependency file generated by the "vopt" tool has either been +removed, is for an older version of the tool or has been corrupted. +Normally re-running vopt on the design will recreate this file and +solve the issue. + + +common Message # 57: +The specified library cannot be found or is not valid. Verify that the +library pathname exists, that it has been created with the "vlib" +command, and that you have the correct permissions for accessing it. + + +common Message # 58: +The specified design unit is missing its version string from the +"_info" file in the library that contains it. Normally, re-compiling +the design unit will fix the problem. + + +common Message # 59: +The specified design unit has been recompiled since the last run of +"vopt". By default the design will be re-optimized before a new +simulation is run. + + +common Message # 60: +There is no additional information for this message. + + +common Message # 61: +Inherited verification unit has not been defined. + + +common Message # 62: +There is no additional information for this message. + + +common Message # 63: +There is no additional information for this message. + + +common Message # 64: +The execution of the 0in command failed. Please check the +associated error log for more details. + + +common Message # 65: +-0in_options needs an additional argument. Please pass the options needed +for the 0in tools with the -0in_options and make sure to have the options in quotes. + + +common Message # 66: +The execution of the executable mentioned in the error message failed. Please +check if the expected arguments were being passed to the executable. + + +common Message # 67: +There is no additional information for this message. + + +common Message # 68: +There is no additional information for this message. + + +common Message # 69: +A typedef with a hierarchical name is required to reference a simple +type identifier within a directly visible interface. +[DOC: IEEE P-180 LRM - Section 4.9 + + +common Message # 70: +Compilation of the C/C++ src files failed. Please check the error log for more details + + +common Message # 71: +Creation of qv_dpi.so failed. Please check the error log for more details. + + +common Message # 72: +The built-in library referenced by the optimized design has changed since +it was originally created. Normally this means the QuestaSim installation +directory has changed, or that design-units have been modified or removed +from the built-in QuestaSim libraries. Typically this should not occur, but +in the event of getting this error, the design needs to be re-optimized +with the "vopt" tool. + + +common Message # 73: +There is no additional information for this message. + + +common Message # 74: +There is no additional information for this message. + + +common Message # 75: +There is no additional information for this message. + + +common Message # 76: +There is no additional information for this message. + + +common Message # 77: +There is no additional information for this message. + + +common Message # 78: +There is no additional information for this message. + + +common Message # 79: +There is no additional information for this message. + + +common Message # 80: +There is no additional information for this message. + + +common Message # 81: +There is no additional information for this message. + + +common Message # 82: +There is no additional information for this message. + + +common Message # 83: +There is no additional information for this message. + + +common Message # 84: +There is no additional information for this message. + + +common Message # 85: +There is no additional information for this message. + + +common Message # 86: +Some functions in packages ieee.numeric_bit and ieee.numeric_std have +formals of type NATURAL. When calling the accelerated versions of these +functions, the bounds checking that would normally occur had the +original VHDL source been called is not performed. This message occurs +when such bounds checking would have produced a fatal error message, so +that the simulation can continue. +The severity of this message can be changed to modify this behavior. +The setting of the INI file variable NumericStdNoWarnings has no +influence on this message. + + +common Message # 87: +There is no additional information for this message. + + +common Message # 88: +There is no additional information for this message. + + +common Message # 89: +Could not verify the operating system being run. Check the QuestaSim +release notes for a list of supported operating systems. + + +common Message # 90: +Check your QuestaSim installation or set your path to point to the +correct location of QuestaSim. + + +common Message # 91: +GNU compilers are not supported on HP-UX. Set the compiler path +to point to the aCC compiler instead. + + +common Message # 92: +Detected improperly formed CppPath variable in modelsim.ini. +Point directly at a compiler executable, such as /usr/bin/g++. + + +common Message # 93: +QuestaSim requires that aCC version 3.45 be installed at /opt/aCC in order +to run SystemC designs on HP-UX. Install the compiler. + + +common Message # 94: +The current operating system is not supported. + +This error message can be suppressed or downgraded to a note or warning. + +common Message # 95: +QuestaSim's SystemC requires that you use a pre-configured g++ compiler. +Your installation directory is missing the compiler installation. +Download and install the appropriate tarball from the ftp site. + + +common Message # 96: +There is no additional information for this message. + + +common Message # 97: +This error may be the result of using an uninitialized object handle, +access type, or dynamic array. Try using the tb command or view the +callstack window to see where the error occurred. + + +common Message # 98: +There is no additional information for this message. + + +common Message # 100: +Real literal syntax requires that a dot (decimal or base point) be +present in the mantissa. A real literal with no dot (i.e., an integer +literal) is accepted but is not LRM-compliant. +[DOC: IEEE Std 1076-1993 VHDL LRM - 13.4.1 Decimal literals] +[DOC: IEEE Std 1076-1993 VHDL LRM - 14.3 Package TEXTIO] + + +common Message # 101: +Real literal syntax requires that the dot (decimal or base point) be +between two digits. A dot as the first character of a real literal is +accepted but is not LRM-compliant. + + +common Message # 102: +Real literal syntax requires that the dot (decimal or base point) be +between two digits. A dot as the last character of a real literal is +accepted but is not LRM-compliant. + + +common Message # 103: +A newline character was found embedded in an extended identifier. +Since a newline character is a non-graphic character that is also a +separator, it is treated as terminating the extended identifier just as +the expected final backslash character would have been. + +This message will be an error with the -pedanticerrors argument. + +common Message # 104: +No characters were found between the initial and terminal backslash +characters that delineate the extended identifier. + +This message will be an error with the -pedanticerrors argument. + +common Message # 105: +Only graphic characters are allowed between the initial and terminal +backslash characters that delineate an extended identifier. + +This message will be an error with the -pedanticerrors argument. + +common Message # 106: +No characters were found after the initial backslash character that +begins an escaped identifier. + + +common Message # 107: +An escaped identifier must contain only printable characters. + + +common Message # 108: +No terminating backslash character was found when parsing an extended +identifier. + + +common Message # 109: +Abstract literal syntax requires that a dot (decimal or base point), +when it appears, be between two digits. + + +common Message # 110: +Abstract literal syntax requires that an underline character, when it +appears, be between two digits. + + +common Message # 111: +No digits or extended digits were present when parsing a number +appearing in a abstract literal. + + +common Message # 112: +Number appearing in an abstract literal must terminate with a digit. + +This error message can be suppressed or downgraded to a note or warning. + +common Message # 113: +Based literal syntax requires that the mantissa part be bracketed by +an initial and terminating '#' or ':' character; both occurrences must +be the same. + + +common Message # 114: +[13.4.1 Decimal literals], line 196: + An exponent for an integer literal must not have a minus sign. +[13.4.2 Based literals], line 220: + An exponent for a based integer literal must not have a minus sign. + + +common Message # 115: +The syntax does not allow a decimal point in the digits of the +exponent part of an abstract literal, and there is no other legal +interpretation that allows a decimal point where it was found. + + +common Message # 116: +The digit is not legal in the literal in which it appears because its +value is greater than or equal to the base of the literal. + + +common Message # 117: +The digit found in an abstract literal is neither a digit nor an +extended digit. + + +common Message # 118: +[13.4.2 Based literals], line 205: + The base must be at least two and at most sixteen. + + +common Message # 119: +The integer value cannot be contained in a signed 32-bit integer. + + +common Message # 120: +The number of elements referenced in an unpacked array concatenation +must match the size of the array it is assigned to. + +This message will be downgraded to a warning with the -permissive argument. +This error message can be suppressed or downgraded to a note or warning. + +common Message # 121: +There is no additional information for this message. + + +common Message # 122: +There is no additional information for this message. + + +common Message # 123: +There is no additional information for this message. + + +common Message # 124: +There is no additional information for this message. + + +common Message # 125: +The shared library has been built on a machine incompatible with +the current machine. Please use compatible machines to compile, link, +and simulate the design. + + +common Message # 129: +QuestaSim uses the system() call to produce intermediate output. +The system() call has failed. Please check the logfile for further +information. + + +common Message # 130: +During a constructor call, the methods that are visible to the constructor +are defined by only the static base classes of the type. A pure virtual method +that is overridden by a later derivation does not have that override available +during the constructor call. + +This error message can be suppressed or downgraded to a note or warning. + +common Message # 131: +This error is the results of using an uninitialized object handle, +access type, or dynamic array. Try using the tb command or view the +callstack window to see where the error occurred. Look for handles +with a null value. + + +common Message # 132: +Refer to QuestaSim User's Guide for a list of supported field types for +structures used at the SystemC-HDL mixed language boundary. + + +common Message # 133: +An rmdir() on the specified directory failed. This message might be +followed by another message that gives more information about the +problem. + + +common Message # 134: +The automatically generated optimized design is locked by a user currently +running vsim. The filename will have a suffix named "__lock", and can +be examined further to determine if the lock is still valid. + + +common Message # 135: +Based literals are always interpreted as positive numbers. In this case, the +literal which was given in binary, octal, or hex is too large to +be represented as a positive integer but can represent a negative value. + + +common Message # 138: +The right "error_handling" cannot be used in an expression that defines the +value of some other right. + + +common Message # 139: +Every right has a set of conditions that can be used in an expression that +defines the value for the right. The condition used is not in this set. +Here are descriptions for all the rights that are recognized by QuestaSim: + RIGHT: decryption + CONDITIONS: license() license_string() + LEGAL VALUES: delegated true false + DEFAULT VALUE: delegated + + RIGHT: error_handling + CONDITIONS: activity toolphase message_severity license() + license_string() + LEGAL VALUES: delegated srcrefs plaintext + DEFAULT VALUE: delegated + + RIGHT: runtime_visibility + CONDITIONS: activity license() license_string() + LEGAL VALUES: delegated interface_names all_names + DEFAULT VALUE: delegated + + RIGHT: child_visibility + CONDITIONS: activity license() license_string() + LEGAL VALUES: delegated allowed denied + DEFAULT VALUE: delegated + + +common Message # 140: +Every right has a set of legal values. The value computed for the right was +not legal for the right; the value "delegated" will be used for this right +instead. +Here are descriptions for all the rights that are recognized by QuestaSim: + RIGHT: decryption + CONDITIONS: license() license_string() + LEGAL VALUES: delegated true false + DEFAULT VALUE: delegated + + RIGHT: error_handling + CONDITIONS: activity toolphase message_severity license() + license_string() + LEGAL VALUES: delegated srcrefs plaintext + DEFAULT VALUE: delegated + + RIGHT: runtime_visibility + CONDITIONS: activity license() license_string() + LEGAL VALUES: delegated interface_names all_names + DEFAULT VALUE: delegated + + RIGHT: child_visibility + CONDITIONS: activity license() license_string() + LEGAL VALUES: delegated allowed denied + DEFAULT VALUE: delegated + + +common Message # 141: +Detected improper path passed with the -cpppath option to sccom +Point directly at a compiler executable, such as /usr/bin/g++. + + +common Message # 142: +vmake does not support SystemC modules. Pass the -ignore option to +get rid of the warning message. + + +common Message # 143: +Reports number of FSMs recognized in design unit. + + +common Message # 144: +Unable to get the compiler version string for the compiler. +Make sure the compiler being used is a valid and supported +compiler as specified in the Users Guide. + + +common Message # 145: +A problem occurred while trying to open the specified file in the +specified mode. This file is used for some internal elaboration technique +Try to suppress this error and run the design + + +common Message # 146: +The SDF file specified is attempting to annotate to a region under a SystemC instances. +Using compiled SDF in this manner is unsupported in the current version +of the simulator. To apply SDF to such a region you should use the normal +options on vsim (e.g. -sdftyp) with -novopt. You may however, annotate to +Verilog and VHDL instances underneath a SystemC instance by directly targeting +those HDL instance. It is the specification of a SystemC instance as the +annotation point that is not supported. + + +common Message # 147: +An uncompiled sdf file was encountered and an attempt to automatically compile +the file failed because of write permissions. Typically compiled sdf output +is placed next to the sdf source file with a .csdf file extension and can +be reused by all simulations. In this case the compiled output file is placed +in a temporary file that will be deleted after simulation completes. + + +common Message # 148: +A compiled sdf file was found not to have the correct delay mode or delay scale +to allow it to be used. Typically compiled sdf output is placed next to the +sdf source file with the delay mode in the file name and a .csdf file extension. +In this case the compiled output file was found to exist but on further examination +it was found to be incompatible. The SDF source file is being recompiled replacing +the output file. + + +common Message # 149: +The library may have been created by a more recent version of QuestaSim/Questa. + + +common Message # 150: +An attempt to suppress the warning message failed because the message + does not correspond to a category of messages in the message +system. + + +common Message # 151: +The function ieee.TO_INTEGER[unsigned RETURN natural] in the packages +ieee.numeric_bit and ieee.numeric_std internally accumulates its result +in a NATURAL variable. At any point during the conversion, if the value +of that variable no longer belongs to subtype NATURAL (because of the +nature of integer computation in the base INTEGER type), then a fatal +error will be produced from original VHDL source. Instead of having the +accelerated version of this function (from which this message occurs) +faithfully reproduce this fatal error (which will always stop a running +simulation and render it un-continuable), this computational overflow is +treated as a warning (by default) because some customers have found it +useful that the conversion continue and return a value that reflects the +value of the 32 least-significant bits of the input. This message can +occur from accelerated versions of these functions: + ieee.numeric_bit.TO_INTEGER[unsigned RETURN natural] + ieee.numeric_bit.TO_INTEGER[signed RETURN integer] + ieee.numeric_std.TO_INTEGER[unsigned RETURN natural] + ieee.numeric_std.TO_INTEGER[signed RETURN integer] +because the would-be fatal error occurs in the unsigned version, and +because the signed version calls the unsigned version. +The severity of this message can be changed to modify this behavior. +The setting of the INI file variable NumericStdNoWarnings has no +influence on this message. + + +common Message # 152: +The LRM explicitly states that default generate block names cannot be used in +hierarchical references. + + +common Message # 153: +The PSL subset operator was not supplied with correct type of operand. + +This error message can be suppressed or downgraded to a note or warning. + +common Message # 154: +The PSL subset operator was not supplied with correct type of operand. +The design unit cannot be simulated. + + +common Message # 155: +There is no additional information for this message. + + +common Message # 156: +There is no additional information for this message. + + +common Message # 157: +There is no additional information for this message. + + +common Message # 158: +The value does not belong to the range defined by the range constraint +of the scalar subtype. + + +common Message # 159: +The mode options -32 and -64 are supported only by a set of programs. +The mode options must be specified directly on the command line. Mode options +specified in command files are ignored. + + +common Message # 160: +This error is the results of calling an undefined foreign function. +Try looking for an earlier warning message about failing to find user-specified +function of the same name. Try using the tb command or view the callstack window +to see where the error occurred. + + +common Message # 161: +Cannot specify -cppinstall and -cpppath to sccom/vopt/vsim on the same command line. +CppPath and CppInstall modelsim.ini variables cannot be specified at the same time. + + +common Message # 162: +The specified GNU compiler is not installed or is not supported. +For a list of supported GNU compiler(s) refer to the Users Guide. + + +common Message # 163: +Empty sequences of the form [*0] cannot have attached match items. + + +common Message # 164: +Directory specified does not exist. If TMPDIR is intended to be set to the +missing directory, make sure that the directory exists and is accessible with +the correct permissions. +Default algorithm will set the TMPDIR value to the predefined macro P_tmpdir in the +standard C-library. If that is not accessible as well, temporary files will be created +in the current working directory. + + +common Message # 165: +There is no additional information for this message. + + +common Message # 166: +Failed to load a Preoptimized Design Unit created using -pdu. +Several reasons for this may exist. For example the dependency file generated +by the "vopt" tool could not be found or was generated by an older tool +version. Normally re-running vopt on the design will recreate the PDU and +solve the issue. It is also possible that the physical path to a library +containing a PDU no longer points to the library. This can occur in a nested +PDU (a PDU containing a PDU). This is due to a PDU fixing all logical +references (including library mappings) to physical references below it. +Soft links can be used to resolve these physical links if necessary. + + +common Message # 167: +Starting in 10.1, objects previously refered to as Black-Boxes/Bboxes +will be refered to as Preoptimized Design Units or PDUs. The command +line option switches have been changed to reflect this name change. + + +common Message # 168: +When a time value is given that is smaller then the current +simulation resolution, the value is truncated to 0 and no run occurred. +Rerun the simulation using a smaller resolution value. + + +common Message # 169: +The value specified as the type of the library was invalid. Valid values +are "directory", "archive" or "flat". + + +common Message # 170: +There is no additional information for this message. + + +common Message # 171: +There is no additional information for this message. + + +common Message # 172: +When using the command-line options -note, -warning, -error, -suppress, or -msglimit +additional options are required, for example: + -suppress [,...] + + +common Message # 173: +A single-quoted string can occur anywhere in an argument file outside +of a commented region. A single quoted-string can span multiple +lines, but it must be terminated before the end of the argument +file. + + +common Message # 174: +The behavior of an embedded newline in an argument file is not defined. + + +common Message # 175: +Parsing arguments file was terminated because recursion was detected while +expanding it. An example of recursion is: +vlog -f filelist +where filelist1 contains: + -f filelist2 +and filelist2 contains: + -f filelist3 +and filelist3 contains: + -f filelist4 +and filelist4 contains: + -f filelist1 + + +common Message # 176: +An unexpected version number was encountered when opening a library. +This library must be converted to the current library version for this release. + + +common Message # 177: +Root causes of stack overflow issues may include a function/task call with deep +recursion, or an automatic function/task using large size formal/local variables, or a +combination of the two. It is recommended that the root cause of the issue in the source +code be identified and recoded. The error message may already contain the call stack +information. If not, please check whether a vsim_stacktrace.vstf is generated, and if available +send it to support for analysis. A quick workaround is to change your shell's stack size limit +by setting it to a number bigger than the required size mentioned in the error message. +Try using shell command 'limit stacksize ' to increase the stack size. + + +common Message # 178: +A potential heap corruption issue has been detected due to excessive stack usage. If you +are working in 32-bit mode, you can move to 64-bit mode to get around this problem. +Ideally you can reduce stack usage by reworking your source code. The error message +may already contain the call stack information. + + +common Message # 179: +This version of this operating system is no longer supported. + + +common Message # 180: +-msglimit flag can be given with one of the options '-all' or '-none'. +Use ' -help' for complete usage. + + +common Message # 181: +The format of the message identifier could not be recognized. + + +common Message # 182: +-stats option syntax is not specified correctly. + + +common Message # 183: +"-stats" arguments provided after -R option are ignored. + + +common Message # 184: +An internal error occurred in the tool. Please contact customer support for further assistance. + + +common Message # 185: +There is no additional information for this message. + + +common Message # 186: +Full support for $countbits functions inside constraint block is not implemented at this time. +$countbits functions with rand control args or functions with more than 2 args are not supported. + + +common Message # 187: +There is no additional information for this message. + + +common Message # 188: +UDP expression coverage has been deprecated. +It will no longer be supported in future releases. + + +common Message # 189: +After a message ID reaches its message reporting limit, message is suppressed +internally by the tool. Limit can be controlled with -msglimitcount option. + + +common Message # 190: +The text of this message depends on the message call site. + + +common Message # 191: +Questa has encountered an unexpected internal error. +Please contact Questa support at http://supportnet.mentor.com. + + +common Message # 192: +UDP expression coverage has been deprecated and will be removed in future releases. + +This error message can be suppressed or downgraded to a note or warning. + +common Message # 193: +Questa has encountered an unexpected internal error. +Please contact Questa support at http://supportnet.mentor.com. + + +common Message # 194: +There is no additional information for this message. + + +common Message # 195: +There is no additional information for this message. + + +common Message # 196: +There is no additional information for this message. + + +common Message # 197: +There is no additional information for this message. + + +common Message # 198: +The indicated feature is under restricted access and requires an additional level +of authorization for its use. Authorized users should have been provided with a +text key and instructions for its use. + + +common Message # 199: +The switch is deprecated and ignored. It will be removed in future releases. + + +common Message # 200: ++cover options can not be used with +flcov options. + + +common Message # 201: +e|c coverage types are not supported in Falcon coverage. + + +common Message # 202: +With +flcov option, only FSM, Toggle, Statement and Branch coverage would be enabled. +Rest of the coverage metrics is not supported in Falcon coverage. + + +common Message # 203: +There are +flcov and +noflcov options specified for some region in the design. +Check vlog/vcom/vopt options to verify. + + +common Message # 204: +Specified option cannot be specified with "-fprofile". + + +common Message # 205: +This feature is not production switch in this version of the product. +Please contact Questa support at http://supportnet.mentor.com to request the access key. + + +common Message # 206: +The specified directory should not contain any files when this operation +is attempted. This warning will become an unsuppressible error in a future +release when the Questa library format changes. Files and directories +that do not originate from Questa tools should not be placed within with +a Questa library object. + + +common Message # 207: +Fprof operation failed - Internal use only + + +common Message # 208: +Fprof operation failed - Internal use only + + +common Message # 209: +Fprof operation failed - Internal use only + + +common Message # 210: +Fprof operation failed - Internal use only + + +common Message # 211: +Logfile cannot be decompressed without .gz extension + + +vcom Message # 1001: +For the -skip and -just options, one or more of the following design +unit indications must be specified: + e or E - entities + a or A - architectures + p or P - packages + b or B - package bodies + c or C - configurations +[DOC: QuestaSim Command Reference - vcom command] + + +vcom Message # 1002: +IEEE Std 1076-1993, 5.2.2 Default binding indication: +In a default binding indication, and in an explicit binding indication +that lacks a generic map aspect, where the entity aspect (whether +default or explicit) implies a design entity that contains formal +generics, a default generic map aspect is assumed within that binding +indication. The default generic map aspect associates each local +generic (if any) of the component declaration corresponding to the +component instantiation with a formal of the same simple name. It is +an error if such a formal does not exist or if its mode and type are +not appropriate for such an association. + +This message will be displayed as a warning if the entity is being +used in a default binding; an elaboration error will occur if this +default binding is used when loading the design. If the default +binding will not be used because an explicit binding in an applicable +component configuration is used instead, then this warning can be +ignored. +The warning version of this message can be suppressed with the +vcom option -nowarn 1. + + +vcom Message # 1003: +No more than the specified number of -noaccel options can be specified. +All -noaccel options encountered after the limit is reached are ignored. + + +vcom Message # 1004: +Design unit dependencies have changed since the last time this design +unit was compiled, therefore it should be recompiled instead of +refreshed. You can force the design unit to be refreshed by using the +-force_refresh option but this might result in incorrect simulation. + + +vcom Message # 1005: +An fseek() on the source file being copied to the specified destination +file failed. This message might be followed by another message that +gives more information about the problem. + + +vcom Message # 1006: +An fread() on the source file being copied to the specified destination +file unexpectedly encountered an end-of-file condition. This message +might be followed by another message that gives more information about +the problem. + + +vcom Message # 1007: +An fread() on the source file being copied to the specified destination +file failed. This message might be followed by another message that +gives more information about the problem. + + +vcom Message # 1008: +An fwrite() on the specified file failed. This message might be followed +by another message that gives more information about the problem. + + +vcom Message # 1009: +The array bounds of the result of the implicit "&" operator are being +computed using the 1993 rules because the 1987 rules are untenable. +This may be important when this result is used as the actual to a +subprogram call (when the formal is an unconstrained array type) +because the formal takes on the bounds of the actual. +[DOC: IEEE Std 1076-1993 VHDL LRM - 7.2.4 Adding operators] +[DOC: IEEE Std 1076-1993 VHDL LRM - 3.2.1.1 Index constraints and discrete ranges] + + +vcom Message # 1010: +The slice is a null slice if the direction of the discrete range is not +the same as that of the object denoted by the prefix of the slice name. +[DOC: IEEE Std 1076-1987 VHDL LRM - 6.5 Slice names] +This was changed to an error in VHDL 1993, see message #1012. + + +vcom Message # 1011: +It is impossible to create a null slice (see warning message #1010) when +the bounds of the discrete range are identical. + + +vcom Message # 1012: +It is an error if the direction of the discrete range of a slice name +is not the same as that of the index range of the array denoted by the +prefix of the slice name. +[DOC: IEEE Std 1076-1993 VHDL LRM - 6.5 Slice names] + + +vcom Message # 1013: +The value of a signal is not defined until after the design hierarchy is +elaborated. Use of the signal name in a declarative item is prohibited +because the value is undefined until the entire design has been +elaborated. +[DOC: IEEE Std 1076-1993 VHDL LRM - 12.3 Elaboration of a declarative part] +[DOC: IEEE Std 1076-2008 VHDL LRM - 14.4.1 General] + +This message will be an error with the -pedanticerrors argument. + +vcom Message # 1014: +When the expression is of an array type, the length of the array must +be known at compile time. The simulator is less restrictive than the +LRM requires as long as the array length of the expression can be +determined in the compiler. +IEEE Std 1076-1993, 8.8 Case statement: + + If the expression is of a one-dimensional character array type, then + the expression must be one of the following: + -- The name of an object whose subtype is locally static + -- An indexed name whose prefix is one of the members of this list + and whose indexing expressions are locally static expressions + -- A slice name whose prefix is one of the members of this list and + whose discrete range is a locally static discrete range + -- A function call whose return type mark denotes a locally static + subtype + -- A qualified expression or type conversion whose type mark + denotes a locally static subtype + + It is an error if the element subtype of the one-dimensional character + array type is not a locally static subtype. + +This message will be an error with the -pedanticerrors argument. + +vcom Message # 1015: +Array index values are represented as 32-bit signed integers. +Computation of an index value has resulted in an overflow; that is, the +index value cannot be represented in 32 bits. This can occur when +an array type has an index subtype of INTEGER and a null array value of +this type has been computed. + + +vcom Message # 1016: +Cannot form an expanded name whose prefix denotes an ENTITY and whose +suffix denotes a named entity in a corresponding ARCHITECTURE BODY of +that ENTITY. +The rules for expanded names require that if the prefix denotes some +named construct, only declarations that appear immediately and textually +within the declarative region of that construct are visible by selection; +such an expanded name can appear only within the construct denoted by the +prefix itself. +VHDL 2008 relaxes this rule so that a prefix that is an ENTITY name can +be used with a suffix that denotes a named entity in the corresponding +ARCHITECTURE body; use compiler switch -2008 in this situation. +IEEE Std 1076-1993, 6.3 Selected names, line 104 +IEEE Std 1076-2008 8.3 Selected names + +This message will be an error with the -pedanticerrors argument. + +vcom Message # 1017: +The () portion of a +acc option design unit +specification has bad syntax or is missing an identifier. +[DOC: QuestaSim Command Reference - vcom command] + + +vcom Message # 1018: +The rules for a VHDL 1987 function subprogram require that any signal +or variable (or any member of thereof) referenced in it be declared in +the declarative region of the function. +[DOC: IEEE Std 1076-1987 VHDL LRM - 2.2 Subprogram Bodies] + + +vcom Message # 1019: +IEEE Std 1076-1993, 6.5 Slice names, line 193: + The prefix of a slice must be appropriate for a one-dimensional + array object. + + +vcom Message # 1020: +VHDL syntax requires exactly one formal part in an association element +when formal part is present. +IEEE Std 1076-1993, 4.3.2.2 Association lists, line 433: + association_element ::= + [ formal_part => ] actual_part + + formal_part ::= + formal_designator + | function_name ( formal_designator ) + | type_mark ( formal_designator ) + + +vcom Message # 1021: +IEEE Std 1076-1987, 4.3.3.2 Association Lists, page 4-11: + formal_part ::= + formal_designator + | function_name ( formal_designator ) + +Syntax for the formal part does not allow a type conversion; +this capability was added for VHDL 1993. + + +vcom Message # 1022: +IEEE Std 1076-1993, 4.3.2.2 Association lists, line 435: + formal_part ::= + formal_designator + | function_name ( formal_designator ) + | type_mark ( formal_designator ) + +IEEE Std 1076-1993, 4.3.2.2 Association lists, line 503: + A formal [designator] may be either an explicitly declared interface + object or member (see Section 3) of such an interface object. + +IEEE Std 1076-1993, Section 3 Types, line 37: + A member of an object is either + -- A slice of the object + -- A subelement of the object + -- A slice of a subelement of the object. + + +vcom Message # 1023: +IEEE Std 1076-1993, 4.3.2.2 Association lists, line 459: + Named associations can be given in any order, but if both positional + and named associations appear in the same association list, then all + positional associations must appear first and at their normal + position. Hence once a named association is used, the rest of the + association list must use only named associations. + + +vcom Message # 1024: +IEEE Std 1076-1993, 4.3.2.2 Association lists, line 508: + Each association element that associates a slice or subelement + (or slice thereof) of an interface object must identify the formal + with a locally static name. + + +vcom Message # 1025: +IEEE Std 1076-1993, 5.2.1.2 Generic map and port map aspects, line 295: + No scalar formal may be associated with more than one actual. No + scalar subelement of any composite formal may be associated more than + once in the same association list. +Similarly at lines 303 and 307. + +IEEE Std 1076-1993, 7.3.3 Function calls, line 465: + For each formal parameter of a function, a function call must specify + exactly one corresponding actual parameter. This actual parameter is + specified either explicitly, by an association element (other than the + actual part OPEN) in the association list or, in the absence of such + and association element, by a default expression (see 4.3.2). +Similarly in 8.6 Procedure call statement, line 381 for procedure calls. + + +vcom Message # 1026: +IEEE Std 1076-1993, 4.3.2.2 Association lists, line 503: + A formal may be either an explicitly declared interface object or + member (see Section 3) of such an interface object. In the former + case, such a formal is said to be associated in whole. In the latter + cases, named association must be used to associate the formal and + actual; the subelements of such a formal are said to be associated + individually. Furthermore, every scalar subelement of the explicitly + declared interface object must be associated exactly once with an + actual (or subelement thereof) in the same association list, and all + such associations must appear in a contiguous sequence within that + association list. + + +vcom Message # 1027: +IEEE Std 1076-1993, 4.3.2.2 Association lists, line 453: + Each association element in an association list associates one actual + designator with the corresponding interface element in the interface + list of a subprogram declaration, component declaration, entity + declaration, or block statement. The corresponding interface element + is determined either by position or name. + + +vcom Message # 1028: +IEEE Std 1076-1993, 5.2.1.2 Generic map and port map aspects, line 295: + No scalar formal may be associated with more than one actual. No + scalar subelement of any composite formal may be associated more than + once in the same association list. +Similarly at lines 303 and 307. + +IEEE Std 1076-1993, 7.3.3 Function calls, line 465: + For each formal parameter of a function, a function call must specify + exactly one corresponding actual parameter. This actual parameter is + specified either explicitly, by an association element (other than the + actual part OPEN) in the association list or, in the absence of such + and association element, by a default expression (see 4.3.2). +Similarly in 8.6 Procedure call statement, line 381 for procedure calls. + + +vcom Message # 1029: +IEEE Std 1076-1993, 6.5 Slice names, line 193: + The prefix of a slice must be appropriate for a one-dimensional + array object. + + +vcom Message # 1030: +IEEE Std 1076-1993, 2.1.1.2 Signal parameters, line 115: + If an actual signal is associated with a signal parameter of any mode, + and if the type of the formal is a scalar type, then it is an error if + the bounds and direction of the subtype denoted by the subtype + indication of the formal are not identical to the bounds and direction + of the subtype denoted by the subtype indication of the actual. + + +vcom Message # 1031: +IEEE Std 1076-1993, 1.1.1.1 Generics, line 74: + It is an error if no actual is specified for a given formal generic + and no default expression is present in the corresponding interface + element. + + +vcom Message # 1032: +IEEE Std 1076-1993, 4.3.2.2 Association lists, line 511: + If an interface element in an interface list includes a default + expression for a formal generic, for a formal port of any mode other + than LINKAGE, or for a formal variable or constant parameter of mode + IN, then any corresponding association list need not include an + association element for that interface element. If the association + element is not included, or if the actual OPEN is given, then the + value of the default expression is used as the actual expression or + signal value in an implicit association element for that interface + element. + + +vcom Message # 1033: +IEEE Std 1076-1993, 4.3.2.2 Association lists, line 511: + If an interface element in an interface list includes a default + expression for a formal generic, for a formal port of any mode other + than LINKAGE, or for a formal variable or constant parameter of mode + IN, then any corresponding association list need not include an + association element for that interface element. If the association + element is not included, or if the actual OPEN is given, then the + value of the default expression is used as the actual expression or + signal value in an implicit association element for that interface + element. + + +vcom Message # 1034: +IEEE Std 1076-1993, 4.3.2.2 Association lists, line 511: + If an interface element in an interface list includes a default + expression for a formal generic, for a formal port of any mode other + than LINKAGE, or for a formal variable or constant parameter of mode + IN, then any corresponding association list need not include an + association element for that interface element. If the association + element is not included, or if the actual OPEN is given, then the + value of the default expression is used as the actual expression or + signal value in an implicit association element for that interface + element. + + +vcom Message # 1035: +IEEE Std 1076-1993, 1.1.1.2 Ports, line 112: + A port of mode IN may be unconnected or unassociated (see 4.3.2.2) + only if its declaration includes a default expression (see 4.3.2). + + +vcom Message # 1036: +IEEE Std 1076-1993, 1.1.1.2 Ports, line 113: + A port of any mode other than IN may be unconnected or unassociated + as long as its type is not an unconstrained array type. + + +vcom Message # 1037: +IEEE Std 1076-1993, 4.3.2.2 Association lists, line 511: + If an interface element in an interface list includes a default + expression for a formal generic, for a formal port of any mode other + than LINKAGE, or for a formal variable or constant parameter of mode + IN, then any corresponding association list need not include an + association element for that interface element. If the association + element is not included, or if the actual OPEN is given, then the + value of the default expression is used as the actual expression or + signal value in an implicit association element for that interface + element. + + +vcom Message # 1038: +IEEE Std 1076-1987, 4.3.3.2 Association Lists: +The standard is not clear on whether or not it is valid to have the +formal part of a named association be in the form of a conversion +function call when the mode of the formal is IN. This is not supported +by vcom -87. + +IEEE Std 1076-1993, 4.3.2.2 Association lists, line 463: + The formal part of a named element association may be in the form of + a function call, where the single argument of the function is the + formal designator itself, if and only if the mode of the formal is + OUT, INOUT, BUFFER, or LINKAGE, and if the actual is not OPEN. + +IEEE Std 1076-2002, 4.3.2.2 Association lists, Page 67: + The formal part of a named association element may be in the form of + a function call, where the single argument of the function is the + formal designator itself, if and only if the mode of the formal is + OUT, INOUT, BUFFER, or LINKAGE, and if the actual is not OPEN. + + +vcom Message # 1039: +IEEE Std 1076-1993, 4.3.2.2 Association lists, line 468: + [T]he formal part of a named element association may be in the form + of a type conversion, where the expression to be converted is the + formal designator itself, if and only if the mode of the formal is + OUT, INOUT, BUFFER, or LINKAGE, and if the actual is not OPEN. + +IEEE Std 1076-2002, 4.3.2.2 Association lists, Page 67: + [T]he formal part of a named association element may be in the form + of a type conversion, where the expression to be converted is the + formal designator itself, if and only if the mode of the formal is + OUT, INOUT, BUFFER, or LINKAGE, and if the actual is not OPEN. + + +vcom Message # 1040: +IEEE Std 1076-1987, 4.3.3.2 Association Lists: +The standard is not clear on whether or not it is valid to have the +actual part of a (named or positional) association element be in the +form of a conversion function call when the mode of the associated +formal is OUT or BUFFER. This is not supported by vcom -87. + +IEEE Std 1076-1993, 4.3.2.2 Association lists, line 474: + [T]he actual part of a (named or positional) element association may + be in the form of a function call, where the single argument of the + function is the actual designator itself, if and only if the mode of + the formal is IN, INOUT, or LINKAGE, and if the actual is not OPEN. + +IEEE Std 1076-2002, 4.3.2.2 Association lists, Page 67: + [T]he actual part of a (named or positional) association element may + be in the form of a function call, where the single argument of the + function is the actual designator itself, if and only if the mode of + the formal is IN, INOUT, or LINKAGE, and if the actual is not OPEN. + + +vcom Message # 1041: +IEEE Std 1076-1993, 4.3.2.2 Association lists, line 481: + [T]he actual part of a (named or positional) element association may + be in the form of a type conversion, where the expression to be type + converted is the actual designator itself, if and only if the mode of + the formal is IN, INOUT, or LINKAGE, and if the actual is not OPEN. + +IEEE Std 1076-2002, 4.3.2.2 Association lists, Page 67: + [T]he actual part of a (named or positional) association element may + be in the form of a type conversion, where the expression to be type + converted is the actual designator itself, if and only if the mode of + the formal is IN, INOUT, or LINKAGE, and if the actual is not OPEN. + + +vcom Message # 1042: +IEEE Std 1076-1993, 4.3.2.2 Association lists, lines 465 and 476: + [T]he function name must denote a function whose single parameter + is of the type of the [formal|actual] and whose result is the type of + the corresponding [actual|formal]. + + +vcom Message # 1043: +IEEE Std 1076-1993, 2.1.1.2 Signal parameters, line 113: + It is an error if a conversion function or type conversion appears in + either the formal part or the actual part of an association element + that associates an actual signal with a formal signal parameter. + + +vcom Message # 1044: +IEEE Std 1076-1993, 2.1.1.2 Signal parameters, line 113: + It is an error if a conversion function or type conversion appears in + either the formal part or the actual part of an association element + that associates an actual signal with a formal signal parameter. + + +vcom Message # 1045: +IEEE Std 1076-1987, 4.3.3.2 Association Lists -- +The standard is not clear on when it is and is not valid to associate +OPEN with a formal. Associating OPEN with formal subelements that are +associated individually is not supported by vcom -87. + +IEEE Std 1076-1993, 4.3.2.2 Association lists line 516: + It is an error if an actual of OPEN is associated with a formal that + is associated individually. An actual of OPEN counts as the single + association allowed for the corresponding formal but does not supply + a constant, signal, or variable (as is appropriate to the object + class of the formal) to the formal. +EXAMPLE: + Using the following association list as an example: + ( OPEN, p1 => OPEN, p2(7 downto 0) => OPEN ) + For the associations "OPEN" and "p1 => OPEN", the formals are + associated in whole; therefore the first two OPEN associations are + legal whether the first formal and p1 are scalars or composites. + For the association "p2(7 downto 0) => OPEN", the subelements of + the formal are associated individually because of the slice + specification; therefore the OPEN association is not legal even + if the slice encompasses the entire range of p2. + + +vcom Message # 1046: +IEEE Std 1076-1993, 4.3.2.2 Association lists, line 516: + It is an error if an actual of OPEN is associated with a formal that + is associated individually. An actual of OPEN counts as the single + association allowed for the corresponding formal but does not supply + a constant, signal, or variable (as is appropriate to the object + class of the formal) to the formal. +EXAMPLE: + Using the following association list as an example: + ( OPEN, p1 => OPEN, p2(7 downto 0) => OPEN ) + For the associations "OPEN" and "p1 => OPEN", the formals are + associated in whole; therefore the first two OPEN association are + legal whether the first formal and p1 are scalars or composites. + For the association "p2(7 downto 0) => OPEN", the subelements of + the formal are associated individually because of the slice + specification; therefore the OPEN association is not legal even + if the slice encompasses the entire range of p2. + + +vcom Message # 1047: +IEEE Std 1076-1993, 2.1.1 Formal parameters, line 48: + In a subprogram call, the actual designator (see 4.3.2.2) associated + with a formal parameter of class signal must be a signal. The actual + designator associated with a formal of class variable must be a + variable. The actual designator associated with a formal of class + constant must be an expression. The actual designator associated with + a formal of class file must be a file. + + +vcom Message # 1048: +IEEE Std 1076-1993, 7.3.2.2 Array aggregates, line 415: + A named association of an array aggregate is allowed to have a choice + that is not locally static, or likewise a choice that is a null range, + only if the aggregate includes a single element association and this + element association has a single choice. An OTHERS choice is locally + static if the applicable index constraint is locally static. +We allow a non-locally static choice if the only other choice in the +aggregate is an OTHERS choice (locally static or not) in the last +association element. Use the -pedanticerrors switch for strict VHDL +compliance to make this an error. + +This message will be an error with the -pedanticerrors argument. + +vcom Message # 1049: +The value of a signal is not defined until after the design hierarchy is +elaborated. Use of the signal name in a generic map is prohibited +because the value is undefined. QuestaSim will allow this, but the +expected results may not be produced. +[DOC: IEEE Std 1076-1993 VHDL LRM - 12.3 Elaboration of a declarative part] + +This message will be an error with the -pedanticerrors argument. + +vcom Message # 1050: +IEEE Std 1076-1993, 4.3.2.2 Association lists, line 463: + The formal part of a named element association may be in the form of + a function call, where the single argument of the function is the + formal designator itself, if and only if the mode of the formal is + OUT, INOUT, BUFFER, or LINKAGE, and if the actual is not OPEN. + In this case, the function name must denote a function whose single + parameter is of the type of the formal and whose result is the type + of the corresponding actual. + +IEEE Std 1076-1993, 4.3.2.2 Association lists, line 474: + Similarly, the actual part of a (named or positional) element + association may be in the form of a function call, where the single + argument of the function is the actual designator itself, if and only + if the mode of the formal is IN, INOUT, or LINKAGE, and if the actual + is not OPEN. In this case, the function name must denote a function + whose single parameter is of the type of the actual, and whose result + is the type of the corresponding formal. In addition, the formal must + not be of class constant for this interpretation to hold (the actual + is interpreted as an expression that is a function call if the class + of the formal is constant). + + +vcom Message # 1051: +IEEE Std 1076-1993, 4.3.2.2 Association lists, line 463: + The formal part of a named element association may be in the form of + a function call, where the single argument of the function is the + formal designator itself, if and only if the mode of the formal is + OUT, INOUT, BUFFER, or LINKAGE, and if the actual is not OPEN. + In this case, the function name must denote a function whose single + parameter is of the type of the formal and whose result is the type + of the corresponding actual. + +IEEE Std 1076-1993, 4.3.2.2 Association lists, line 474: + Similarly, the actual part of a (named or positional) element + association may be in the form of a function call, where the single + argument of the function is the actual designator itself, if and only + if the mode of the formal is IN, INOUT, or LINKAGE, and if the actual + is not OPEN. In this case, the function name must denote a function + whose single parameter is of the type of the actual, and whose result + is the type of the corresponding formal. In addition, the formal must + not be of class constant for this interpretation to hold (the actual + is interpreted as an expression that is a function call if the class + of the formal is constant). + + +vcom Message # 1052: +IEEE Std 1076-1993, 4.3.2.2 Association lists, line 463: + The formal part of a named element association may be in the form of + a function call, where the single argument of the function is the + formal designator itself, if and only if the mode of the formal is + OUT, INOUT, BUFFER, or LINKAGE, and if the actual is not OPEN. + In this case, the function name must denote a function whose single + parameter is of the type of the formal and whose result is the type + of the corresponding actual. + +IEEE Std 1076-1993, 4.3.2.2 Association lists, line 474: + Similarly, the actual part of a (named or positional) element + association may be in the form of a function call, where the single + argument of the function is the actual designator itself, if and only + if the mode of the formal is IN, INOUT, or LINKAGE, and if the actual + is not OPEN. In this case, the function name must denote a function + whose single parameter is of the type of the actual, and whose result + is the type of the corresponding formal. In addition, the formal must + not be of class constant for this interpretation to hold (the actual + is interpreted as an expression that is a function call if the class + of the formal is constant). + + +vcom Message # 1053: +IEEE Std 1076-1993, 12.6.2 Propagation of signal values, line 498: + The driving value of a formal part is obtained by evaluating the + formal part as follows: If no conversion function or type conversion + is present in the formal part, then the driving value of the formal + part is the driving value of the signal denoted by the formal + designator. Otherwise, the driving value of the formal part is the + value obtained by applying either the conversion function or type + conversion (whichever is contained in the formal part) to the driving + value of the signal denoted by the formal designator. + +This necessitates that the FUNCTION used as a conversion function in the +formal part of an association element have a class constant formal +parameter as its (single) formal parameter because otherwise (with a +formal parameter of class signal) there could be no guarantee that only +the driving value of the signal denoted by the formal designator was +being used. + + +vcom Message # 1054: +IEEE Std 1076-1993, 12.6.2 Propagation of signal values, line 521: + If S is a connected port of mode IN or INOUT, then the effective + value of S is the same as the effective value of the actual part + of the association element that associates an actual with S (see + 4.3.2.2). The effective value of an actual part is obtained by + evaluating the actual part, using the effective value of the signal + denoted by the actual designator in place of the actual designator. + +This necessitates that the FUNCTION used as a conversion function in the +actual part of an association element have a class constant formal +parameter as its (single) formal parameter because otherwise (with a +formal parameter of class signal) there could be no guarantee that only +the effective value of the signal denoted by the actual designator was +being used. + + +vcom Message # 1055: +IEEE Std 1076-1987, 4.3.2 File Declarations: +The only modes allowed in an external file association are in and out. + + +vcom Message # 1056: +IEEE Std 1076-2008, 10.9 Case statement: + [case_label:] case[?] expression is + case_statement_alternative {case_statement_alternative} + end case[?] [case_label] ; + A case statement shall include the question mark delimiter either in + both places, in which case the case statement is called a matching case + statement, or in neither place, in which case the case statement is + called an ordinary case statement. + + +vcom Message # 1057: +The function has more than one formal argument, which makes it ineligible +to be a conversion function. In VHDL 1993 and later, this is legal only +if the function call is globally static and the port is of mode IN. In +VHDL 2008, this is legal for mode IN ports, but the semantics depend on +the expression being globally static or not. +This warning is for informational purposes only. +IEEE Std 1076-1993, 1.1.1.2 Ports +IEEE Std 1076-2008, 6.5.6.3 Port clauses + + +vcom Message # 1060: +IEEE Std 1076-1993, 7.3.2 Aggregates, line 389: + An element association with the choice OTHERS is allowed in either + an array aggregate or a record aggregate if the association appears + last and has this single choice; it specifies all remaining elements, + if any. + + +vcom Message # 1061: +IEEE Std 1076-1993, 7.3.2 Aggregates, line 389: + An element association with the choice OTHERS is allowed in either + an array aggregate or a record aggregate if the association appears + last and has this single choice; it specifies all remaining elements, + if any. + + +vcom Message # 1062: +IEEE Std 1076-1993, 7.3.2 Aggregates, line 380: + Both named and positional associations can be used in the same + aggregate, with all positional associations appearing first (in + textual order) and all named associations appearing next (in any + order, except that no associations may follow an OTHERS association). + + +vcom Message # 1063: +Each element of the value defined by an aggregate must be represented +once and only once in the aggregate. +[DOC: IEEE Std 1076-1993 VHDL LRM - 7.3.2 Aggregates] + + +vcom Message # 1064: +If the choice OTHERS is given as a choice of a record aggregate, it must +represent at least one element. +[DOC: IEEE Std 1076-1993 VHDL LRM - 7.3.2.1 Record aggregates] + +This message will be an error with the -pedanticerrors argument. + +vcom Message # 1065: +The record element name specified in a choice of an element association +in a record aggregate does not have a corresponding record element in +the record type. +Similarly, in a record constraint in a subtype indication, the named +element is not an element of the record type. + + +vcom Message # 1066: +IEEE Std 1076-1993, 7.3.2 Aggregates, line 392: + Each element of the value defined by an aggregate must be represented + once and only once in the aggregate. + + +vcom Message # 1067: +A choice in a named element association of an aggregate of a record +type must be either an element simple name or the reserved word OTHERS. +[DOC: IEEE Std 1076-1993 VHDL LRM - 7.3.2 Aggregates] + + +vcom Message # 1068: +IEEE Std 1076-1993, 3.2.1 Array types, line 286: + The name for an element of an array uses one or more index values + belonging to specified discrete types. + +IEEE Std 1076-1993, 7.3.2.2 Array aggregates, line 407: + For an aggregate of a one-dimensional array type, each choice must + specify values of the index type[.] + + +vcom Message # 1069: +IEEE Std 1076-1993, 7.3.2.2 Array aggregates, line 414: + Apart from a final element association with the single choice OTHERS, + the rest (if any) of the element associations of an array aggregate + must be either all positional or all named. + + +vcom Message # 1070: +A choice must be of the same type as the index subtype of the base +array type. Since the bounds are not the same type, at least one +of them is not of the same type as the index subtype. +[DOC: IEEE Std 1076-1993 VHDL LRM - 7.3.2.2 Array aggregates] + + +vcom Message # 1071: +A choice must be of the same type as the index subtype of the base +array type. +[DOC: IEEE Std 1076-1993 VHDL LRM - 7.3.2.2 Array aggregates] + + +vcom Message # 1072: +IEEE Std 1076-1993, 7.3.2.2 Array aggregates, line 415: + A named association of an array aggregate is allowed to have a choice + that is not locally static, or likewise a choice that is a null range, + only if the aggregate includes a single element association and this + element association has a single choice. An OTHERS choice is locally + static if the applicable index constraint is locally static. + + +vcom Message # 1073: +IEEE Std 1076-1993, 7.3.2.2 Array aggregates, line 415: + A named association of an array aggregate is allowed to have a choice + that is not locally static, or likewise a choice that is a null range, + only if the aggregate includes a single element association and this + element association has a single choice. An OTHERS choice is locally + static if the applicable index constraint is locally static. +We allow a non-locally static choice if the only other choice in the +aggregate is an OTHERS choice (locally static or not) in the last +association element. Use the -pedanticerrors switch for strict VHDL +compliance to make this an error. + + +vcom Message # 1074: +IEEE Std 1076-1993, 7.3.2.2 Array aggregates, line 415: + A named association of an array aggregate is allowed to have a choice + that is not locally static, or likewise a choice that is a null range, + only if the aggregate includes a single element association and this + element association has a single choice. An OTHERS choice is locally + static if the applicable index constraint is locally static. +QuestaSim allows a non-locally static OTHERS choice if all the other +element associations are positional associations, or if all the other +choices in named associations are locally static, or if there only one +other non-locally static choice. Use the -pedanticerrors switch for +strict VHDL compliance to make this an error. + +This message will be an error with the -pedanticerrors argument. + +vcom Message # 1075: +IEEE Std 1076-1993, 7.3.2 Aggregates, line 392: + Each element of the value defined by an aggregate must be represented + once and only once in the aggregate. + + +vcom Message # 1076: +IEEE Std 1076-2002, 7.3.2.2 Array aggregates, page 109: + The subtype of an array aggregate that has an OTHERS choice must be + determinable from the context. That is, an array aggregate with an + OTHERS choice must appear only in one of the following contexts: + + a) As an actual associated with a formal parameter or formal generic + declared to be of a constrained array subtype (or subelement + thereof) + + b) As the default expression defining the default initial value of a + port declared to be of a constrained array subtype + + c) As the result expression of a function, where the corresponding + function result type is a constrained array subtype + + d) As a value expression in an assignment statement, where the + target is a declared object, and the subtype of the target is a + constrained array subtype (or subelement of such a declared + object) + + e) As the expression defining the initial value of a constant or + variable object, where that object is declared to be of a + constrained array subtype + + f) As the expression defining the default values of signals in a + signal declaration, where the corresponding subtype is a + constrained array subtype + + g) As the expression defining the value of an attribute in an + attribute specification, where that attribute is declared to be of + a constrained array subtype + + h) As the operand of a qualified expression whose type mark denotes + a constrained array subtype + + i) As a subaggregate nested within an aggregate, where that aggregate + itself appears in one of these contexts + + +vcom Message # 1077: +In a type conversion between array types, a check is made that any +constraint on the element subtype is the same for the operand array type +as for the target array type. +For an element subtype that is a scalar subtype, the bounds of +the range constraint must match those of the subtype of the operand. +For an element subtype that is an array subtype, the bounds of +each index range in the index constraint must match those of the +operand. +[DOC: IEEE Std 1076-1993 VHDL LRM - 7.3.5 Type conversions], line 490 +Allowed if target type element constraint is a superset of the operand +type element constraint. + +This message will be an error with the -pedanticerrors argument. + +vcom Message # 1078: +The name is ambiguous according to the visibility rules. +IEEE Std 1076-1993, 10.4 Use clauses, line 234: + Potentially visible declarations that have the same designator are not + made directly visible unless each of them is either an enumeration + literal specification or the declaration of a subprogram (either by a + subprogram declaration or by an implicit declaration). + + +vcom Message # 1079: +The left and right bounds of a range expression (of the form +simple_expression direction simple_expression) must either +have the same type, or either both be of some integer type or +both be of some floating point type. +[DOC: IEEE Std 1076-1993 VHDL LRM - 3.1.2 Integer types] +[DOC: IEEE Std 1076-1993 VHDL LRM - 3.1.3 Physical types] +[DOC: IEEE Std 1076-1993 VHDL LRM - 3.1.4 Floating point types] + + +vcom Message # 1080: +For a discrete range used in a constrained array definition and defined +by a range, an implicit conversion to the predefined type INTEGER is +assumed if each bound is either a numeric literal or an attribute, and +if the type of both bounds (prior to the implicit conversion) is the +type universal_integer. +Otherwise, both bounds must be of the same discrete type, other than +universal_integer; this type must be determined independently of the +context, but using the fact that the type must be discrete and that +both bounds must have the same type. These rules also apply to a +discrete range used in an iteration scheme (see 8.9) or a generation +scheme (see 9.7). +[DOC: IEEE Std 1076-1993 VHDL LRM - 3.2.1.1. Index constraints and discrete ranges] + + +vcom Message # 1081: +For a discrete range used in a constrained array definition and defined +by a range, an implicit conversion to the predefined type INTEGER is +assumed if each bound is either a numeric literal or an attribute, and +if the type of both bounds (prior to the implicit conversion) is the +type universal_integer. +Otherwise, both bounds must be of the same discrete type, other than +universal_integer; this type must be determined independently of the +context, but using the fact that the type must be discrete and that +both bounds must have the same type. These rules also apply to a +discrete range used in an iteration scheme (see 8.9) or a generation +scheme (see 9.7). +[DOC: IEEE Std 1076-1993 VHDL LRM - 3.2.1.1. Index constraints and discrete ranges] + + +vcom Message # 1082: +For a discrete range used in a constrained array definition and defined +by a range, an implicit conversion to the predefined type INTEGER is +assumed if each bound is either a numeric literal or an attribute, and +if the type of both bounds (prior to the implicit conversion) is the +type universal_integer. +Otherwise, both bounds must be of the same discrete type, other than +universal_integer; this type must be determined independently of the +context, but using the fact that the type must be discrete and that +both bounds must have the same type. These rules also apply to a +discrete range used in an iteration scheme (see 8.9) or a generation +scheme (see 9.7). +[DOC: IEEE Std 1076-1993 VHDL LRM - 3.2.1.1. Index constraints and discrete ranges] + + +vcom Message # 1083: +The implicit operator "=" (likewise "/=") will return FALSE +(likewise TRUE) if the operands have different array index range +lengths at any position in the index constraint. + + +vcom Message # 1084: +If a range constraint is used in a subtype indication, the type of the +expressions (likewise, of the bounds of a range attribute) must be the +same as the base type of the type mark of the subtype indication. +[DOC: IEEE Std 1076-1993 VHDL LRM - 3.1 Scalar types] + + +vcom Message # 1085: +If a range constraint is used in a subtype indication, the type of the +expressions (likewise, of the bounds of a range attribute) must be the +same as the base type of the type mark of the subtype indication. +[DOC: IEEE Std 1076-1993 VHDL LRM - 3.1 Scalar types] + +This message will be an error with the -pedanticerrors argument. + +vcom Message # 1086: +The bounds of the discrete range define those of the slice and must be +of the type of the index of the array. +[DOC: IEEE Std 1076-1993 VHDL LRM - 6.5 Slice names] + + +vcom Message # 1087: +The bounds of the discrete range define those of the slice and must be +of the type of the index of the array. +[DOC: IEEE Std 1076-1993 VHDL LRM - 6.5 Slice names] + + +vcom Message # 1088: +Index expression(s) of an indexed name cannot be range(s). +[DOC: IEEE Std 1076-1993 VHDL LRM - 6.4 Indexed names] + + +vcom Message # 1089: +A slice name denotes a one-dimensional array composed of a sequence of +consecutive elements of another one-dimensional array. The prefix must +be of a one-dimensional array type, and there must be exactly one +discrete range. +[DOC: IEEE Std 1076-1993 VHDL LRM - 6.5 Slice names] + + +vcom Message # 1090: +A process that has no sensitivity list, contains no wait statements, +and contains no calls to procedures that contain wait statements will +execute forever without advancing time. + +IEEE Std 1076-2002, 9.2 Process statement: + The execution of a process statement consists of the repetitive + execution of its sequence of statements. After the last statement in + the sequence of statements of a process statement is executed, + execution will immediately continue with the first statement in the + sequence of statements. + +This message can be suppressed with the vcom option -nowarn 2. + + +vcom Message # 1091: +The reserved word POSTPONED must not appear at the end of a process that +does not start with the reserved word POSTPONED. + +IEEE Std 1076-2002, 9.2 Process statement: + + If the reserved word POSTPONED precedes the initial reserved word + PROCESS, the process statement defines a postponed process; otherwise, + the process statement defines a nonpostponed process. + + If the reserved word POSTPONED appears at the end of a process + statement, the process must be a postponed process. + + +vcom Message # 1092: +Signals in process sensitivity lists must be static. +IEEE Std 1076-2002, 9.2 Process statement: + It is an error if any name that does not denote a static signal name + (see 6.1) for which reading is permitted appears in the sensitivity + list of a process statement. + + +vcom Message # 1093: +EXIT and NEXT statements cannot appear outside of a LOOP statement. + +IEEE Std 1076-2002, 8.10 Next statement: + + A next statement is used to complete the execution of one of the + iterations of an enclosing loop statement (called "loop" in the + following text). + + A next statement with a loop label is only allowed within the labeled + loop and applies to that loop; a next statement without a loop label + is only allowed within a loop and applies only to the innermost + enclosing loop (whether labeled or not). + +IEEE Std 1076-2002, 8.11 Exit statement: + + An exit statement is used to complete the execution of an enclosing + loop statement (called "loop" in the following text). + + An exit statement with a loop label is only allowed within the labeled + loop and applies to that loop; an exit statement without a loop label + is only allowed within a loop and applies only to the innermost + enclosing loop (whether labeled or not). + + +vcom Message # 1094: +When a label is specified with an EXIT or NEXT statement, it must be the +label of a LOOP statement. + +IEEE Std 1076-2002, 8.10 Next statement: + + A next statement with a loop label is only allowed within the labeled + loop and applies to that loop; a next statement without a loop label + is only allowed within a loop and applies only to the innermost + enclosing loop (whether labeled or not). + +IEEE Std 1076-2002, 8.11 Exit statement: + + An exit statement with a loop label is only allowed within the labeled + loop and applies to that loop; an exit statement without a loop label + is only allowed within a loop and applies only to the innermost + enclosing loop (whether labeled or not). + + +vcom Message # 1095: +When a label is specified with an EXIT or NEXT statement, the EXIT or +NEXT statement must be inside of the specified LOOP statement. + +IEEE Std 1076-2002, 8.10 Next statement: + + A next statement with a loop label is only allowed within the labeled + loop and applies to that loop; a next statement without a loop label + is only allowed within a loop and applies only to the innermost + enclosing loop (whether labeled or not). + +IEEE Std 1076-2002, 8.11 Exit statement: + + An exit statement with a loop label is only allowed within the labeled + loop and applies to that loop; an exit statement without a loop label + is only allowed within a loop and applies only to the innermost + enclosing loop (whether labeled or not). + + +vcom Message # 1096: +The specified name was referenced as a label but was not found to be a +label of any statement. A name referenced as a label name must be the name +of a label on a statement appropriate to the reference. + + +vcom Message # 1097: +The alias designator was found to be a string literal. This is allowed +only in VHDL 1993 and later, only if the string literal actually +represents an operator symbol, and only if the name (being aliased) +denotes a function. Use VHDL 1993 or later +(vcom options -93, -2002, etc.). + + +vcom Message # 1098: +The alias designator was found to be a character literal. This is +allowed only in VHDL 1993 and later, and only if the name (being +aliased) denotes an enumeration literal of some enumeration type. +Use VHDL 1993 or later (vcom options -93, -2002, etc.). + + +vcom Message # 1099: +VHDL 1987 does not allow signatures. +Use VHDL93 or later (vcom options -93, -2002, etc.). + +This message will be an error with the -pedanticerrors argument. + +vcom Message # 1100: +VHDL 1987 does not allow END ARCHITECTURE. +Remove ARCHITECTURE or use VHDL 1993 or later. + +This message will be an error with the -pedanticerrors argument. + +vcom Message # 1101: +Use VHDL93 or later (vcom options -93, -2002, etc.). + +This message will be an error with the -pedanticerrors argument. + +vcom Message # 1102: +It is legal VHDL to have a nested protected type declaration with the +same name as an enclosing protected type (body) declaration. However, +because protected type declarations are not scopes in the design pathname +sense, this scenario will not lend itself well to the formation of design +pathnames. In particular, only the outermost "this" object will be +found. + + +vcom Message # 1103: +Use VHDL93 or later (vcom options -93, -2002, etc.). + +This message will be an error with the -pedanticerrors argument. + +vcom Message # 1104: +VHDL 1987 does not allow END CONFIGURATION. +Remove CONFIGURATION or use VHDL93 or later (vcom options -93, -2002, etc.). + +This message will be an error with the -pedanticerrors argument. + +vcom Message # 1105: +The syntax for an entity aspect requires that the name following the +reserved word ENTITY be the name of an entity declaration (followed +optionally by an architecture identifier in parentheses). + + +vcom Message # 1106: +The syntax for an entity aspect requires that the name following the +reserved word CONFIGURATION be the name of a configuration declaration. + + +vcom Message # 1107: +Use VHDL 1993 or later (vcom options -93, -2002, etc.). + +This message will be an error with the -pedanticerrors argument. + +vcom Message # 1108: +Use VHDL 1993 or later (vcom options -93, -2002, etc.). + +This message will be an error with the -pedanticerrors argument. + +vcom Message # 1109: +Use VHDL 1993 or later (vcom options -93, -2002, etc.). + +This message will be an error with the -pedanticerrors argument. + +vcom Message # 1110: +Use VHDL 1993 or later (vcom options -93, -2002, etc.). + +This message will be an error with the -pedanticerrors argument. + +vcom Message # 1111: +Remove ENTITY or use VHDL93 or later (vcom options -93, -2002, etc.). + +This message will be an error with the -pedanticerrors argument. + +vcom Message # 1112: +Recompile using VHDL 1993 or later (vcom options -93, -2002, etc.). + + +vcom Message # 1113: +Use VHDL 1993 or later (vcom options -93, -2002, etc.). + + +vcom Message # 1114: +Use VHDL 1993 or later (vcom options -93, -2002, etc.). + + +vcom Message # 1115: +The syntax for a function specification requires a type mark, not a +subtype indication, after the reserved word RETURN. A type mark is the +name of a type or subtype and does not contain a constraint. + + +vcom Message # 1116: +VHDL 1987 does not allow END PACKAGE BODY. Remove PACKAGE BODY or use +VHDL 1993 or later (vcom options -93, -2002, etc.). + +This message will be an error with the -pedanticerrors argument. + +vcom Message # 1117: +VHDL 1987 does not allow END PACKAGE. Remove PACKAGE or use +VHDL93 or later (vcom options -93, -2002, etc.). + +This message will be an error with the -pedanticerrors argument. + +vcom Message # 1118: +A function defined using VHDL 1987 cannot call a procedure that +references a signal or variable (or member of such) that has not been +declared within the declarative region formed by the function or the +declarative region formed by the procedure. +Also, calling an IMPURE FUNCTION from a VHDL 1987 FUNCTION is not +allowed. +[DOC: IEEE Std 1076-1987 VHDL LRM - 2.2 Subprogram Bodies] + + +vcom Message # 1119: +A pure function cannot be the parent of an impure function; nor can it +be the parent of a procedure that references a signal or variable (or +member of such) that has not been declared within the declarative region +formed by the pure function or the declarative region formed by the +procedure. Furthermore, a procedure whose parent is a pure function +cannot contain a reference to a FILE object or to a shared variable. +[DOC: IEEE Std 1076-1993 VHDL LRM - 2.2 Subprogram bodies] + + +vcom Message # 1120: +Several places in VHDL that allow subtype indications do not allow the +subtype indication to specify a resolution function. These places are: + 1) As part of an allocator + [DOC: IEEE Std 1076-2002 VHDL LRM - 7.3.6 Allocators] + 2) As part of the access type declaration + [DOC: IEEE Std 1076-2002 VHDL LRM - 3.3 Access types] + + +vcom Message # 1121: +A range constraint in a type definition must be locally static. +[DOC: IEEE Std 1076-2002 VHDL LRM - 3.1.2 Integer types] +[DOC: IEEE Std 1076-2002 VHDL LRM - 3.1.3 Physical types] +[DOC: IEEE Std 1076-2002 VHDL LRM - 3.1.4 Floating point types] + + +vcom Message # 1122: +Remove the name or label or use VHDL 1993 or later +(vcom options -93, -2002, etc.). + +This message will be an error with the -pedanticerrors argument. + +vcom Message # 1123: +Remove IS or use VHDL 1993 or later (vcom options -93, -2002, etc.). + +This message will be an error with the -pedanticerrors argument. + +vcom Message # 1124: +Remove BEGIN or use VHDL 1993 or later (vcom options -93, -2002, etc.). + +This message will be an error with the -pedanticerrors argument. + +vcom Message # 1125: +VHDL 1987 does not allow END PROCEDURE. Remove PROCEDURE or use VHDL 1993 +or later (vcom options -93, -2002, etc.). + +This message will be an error with the -pedanticerrors argument. + +vcom Message # 1126: +VHDL 1987 does not allow END FUNCTION. Remove FUNCTION or use VHDL 1993 +or later (vcom options -93, -2002, etc.). + +This message will be an error with the -pedanticerrors argument. + +vcom Message # 1127: +While attempting to find a default binding for an instance that was not +specifically bound, a matching entity was found but not used because it +is out of date relative to at least one of it dependencies and needs to +be recompiled. +The warning version of this message can be suppressed with the vcom +option -nowarn 1. + + +vcom Message # 1128: +In generate statements, declarative items must be separated from concurrent +statements by the reserved word BEGIN. + +This message will be an error with the -pedanticerrors argument. + +vcom Message # 1129: +While attempting to bind a component to an entity, the type of the +specified generic in the component declaration was found to be different +from the matching formal generic of the specified entity. + +This message will be displayed as a warning if the entity is being +used in a default binding; an elaboration error will occur if this +default binding is used when loading the design. If the default +binding will not be used because an explicit binding in an applicable +component configuration is used instead, then this warning can be +ignored. +The warning version of this message can be suppressed with the +vcom option -nowarn 1. +[DOC: IEEE Std 1076-1993 VHDL LRM - 5.2.2 Default binding indication] + +This error message can be suppressed or downgraded to a note or warning. + +vcom Message # 1130: +IEEE Std 1076-1993, 5.2.2 Default binding indication: +In a default binding indication, and in an explicit binding indication +that lacks a port map aspect, where the entity aspect (whether default +or explicit) implies a design entity that contains formal ports, a +default port map aspect is assumed within that binding indication. +The default port map aspect associates each local port (if any) of the +component declaration corresponding to the component instantiation with +a formal of the same simple name. Any unassociated formals are +associated with the actual designator OPEN. This means that these +formals are unconnected, which is not legal in this situation because +of the following requirement: +IEEE Std 1076-1993, 1.1.1.2 Ports, line 112: + A port of mode IN may be unconnected or unassociated (see 4.3.2.2) + only if its declaration includes a default expression (see 4.3.2). + A port of any mode other than IN may be unconnected or unassociated + as long as its type is not an unconstrained array type. + +This message will be displayed as a warning if the entity is being +used in a default binding; an elaboration error will occur if this +default binding is used when loading the design. If the default +binding will not be used because an explicit binding in an applicable +component configuration is used instead, then this warning can be +ignored. +The warning version of this message can be suppressed with the +vcom option -nowarn 1. + +This error message can be suppressed or downgraded to a note or warning. + +vcom Message # 1131: +IEEE Std 1076-1993, 5.2.2 Default binding indication: +In a default binding indication, and in an explicit binding indication +that lacks a port map aspect, where the entity aspect (whether default +or explicit) implies a design entity that contains formal ports, a +default port map aspect is assumed within that binding indication. +The default port map aspect associates each local port (if any) of the +component declaration corresponding to the component instantiation with +a formal of the same simple name. It is an error if such a formal does +not exist or if its mode and type are not appropriate for such an +association. + +This message will be displayed as a warning if the entity is being +used in a default binding; an elaboration error will occur if this +default binding is used when loading the design. If the default +binding will not be used because an explicit binding in an applicable +component configuration is used instead, then this warning can be +ignored. +The warning version of this message can be suppressed with the +vcom option -nowarn 1. + + +vcom Message # 1132: +Every local port of a component must be associated as an actual in a +port map aspect appearing in a binding indication. This rule applies +as-specified in VHDL 1987; the introduction of incremental binding in +VHDL 1993 means the application of this rule must be performed on the +effective port map aspect formed from that of the primary binding and +that of the incremental binding (if any). +The same rule for generics has never been enforced and was in fact +eliminated for VHDL 1993 and later. +[DOC: IEEE Std 1076-1987 VHDL LRM - 5.2.1.2 Generic Map And Port Map Aspects] + + +vcom Message # 1133: +IEEE Std 1076-1993, 5.2.2 Default binding indication: +In a default binding indication, and in an explicit binding indication +that lacks a port map aspect, where the entity aspect (whether default +or explicit) implies a design entity that contains formal ports, a +default port map aspect is assumed within that binding indication. +The default port map aspect associates each local port (if any) of the +component declaration corresponding to the component instantiation with +a formal of the same simple name. It is an error if such a formal does +not exist or if its mode and type are not appropriate for such an +association. + +This message will be displayed as a warning if the entity is being +used in a default binding; an elaboration error will occur if this +default binding is used when loading the design. If the default +binding will not be used because an explicit binding in an applicable +component configuration is used instead, then this warning can be +ignored. +The warning version of this message can be suppressed with the +vcom option -nowarn 1. + + +vcom Message # 1134: +IEEE Std 1076-1993, 5.2.2 Default binding indication: +In a default binding indication, and in an explicit binding indication +that lacks a port map aspect, where the entity aspect (whether default +or explicit) implies a design entity that contains formal ports, a +default port map aspect is assumed within that binding indication. +The default port map aspect associates each local port (if any) of the +component declaration corresponding to the component instantiation with +a formal of the same simple name. It is an error if such a formal does +not exist or if its mode and type are not appropriate for such an +association. Compatible port modes are as follows: + + Formal (Entity) Port Mode Local (Component) Port Mode + ------------------------- --------------------------- + IN IN, INOUT, BUFFER + OUT OUT, INOUT (BUFFER - VHDL 2002 and + Verilog only) + INOUT INOUT (BUFFER - VHDL 2002 only) + BUFFER BUFFER (OUT and INOUT - VHDL 2002 only) + LINKAGE any mode + +This message will be displayed as a warning if the entity is being +used in a default binding; an elaboration error will occur if this +default binding is used when loading the design. If the default +binding will not be used because an explicit binding in an applicable +component configuration is used instead, then this warning can be +ignored. +The warning version of this message can be suppressed with the +vcom option -nowarn 1. +[DOC: IEEE Std 1076-2002 VHDL LRM - 1.1.1.2 Ports] + + +vcom Message # 1135: +The syntax for declaring subprogram parameters that are files changed +from the 1987 to the 1993 version of the VHDL language. File parameters +must have the reserved word FILE before their declaration. + +This message will be an error with the -pedanticerrors argument. + +vcom Message # 1136: +The specified name was referenced but was not found. This indicates +that either the name specified does not exist or is not visible at this +point in the code. + + +vcom Message # 1137: +The expression did not satisfy the requirements for a CASE expression +or a selected signal assignment expression of an array type. +IEEE Std 1076-1993, 8.8 Case statement: + + If the expression is of a one-dimensional character array type, then + the expression must be one of the following: + -- The name of an object whose subtype is locally static + -- An indexed name whose prefix is one of the members of this list + and whose indexing expressions are locally static expressions + -- A slice name whose prefix is one of the members of this list and + whose discrete range is a locally static discrete range + -- A function call whose return type mark denotes a locally static + subtype + -- A qualified expression or type conversion whose type mark + denotes a locally static subtype + + It is an error if the element subtype of the one-dimensional character + array type is not a locally static subtype. + +This message will be an error with the -pedanticerrors argument. + +vcom Message # 1138: +Attributes must be declared with an attribute declaration before use +in an attribute specification. + + +vcom Message # 1139: +The identifier did not denote the name of an attribute. + + +vcom Message # 1140: +The 1993 version of VHDL standardized on the attribute FOREIGN for +foreign subprograms and design units. As a result, a declaration +of the attribute FOREIGN was added to the standard package. +If another package declares the attribute FOREIGN and is included via +a USE clause, both definitions of the attribute should be hidden. +For upward compatibility the attribute declaration from the standard +package is being used. +Use the -pedanticerrors option to force strict language compliance. + + +vcom Message # 1141: +The syntax requires a component name. The name given does not denote a +component declaration. + + +vcom Message # 1142: +The type of the actual designator associated with the formal port of a +Verilog module is either not a supported type, or could not be +determined. When the type cannot be determined, it is usually because +the subelements of an individually associated formal are not all of the +same type, making determining the array type impossible. + + +vcom Message # 1143: +The expression is legal under VHDL-1987 but ambiguous under VHDL-1993 +semantics. Either use qualified expressions for the types of parameters +or compile using VHDL-1987. + + +vcom Message # 1144: +The value either does not belong to the range defined by the range +constraint of a scalar subtype or is not a legal position number in an +enumeration type. + + +vcom Message # 1145: +The value either does not belong to the range defined by the range +constraint of a scalar subtype or is not a legal position number in an +enumeration type. + + +vcom Message # 1146: +The type either is a scalar subtype defined with a null range or is a +composite type that contains a subelement of such a scalar subtype. +No object of such a type can exist because no value can belong to a null +range constraint of a scalar subtype. + + +vcom Message # 1147: +The discrete range in the parameter specification of a FOR GENERATE +statement must be a (globally) static range. It cannot depend on a +signal value or other non-static value. + +This message will be an error with the -pedanticerrors argument. + +vcom Message # 1148: +The condition in an IF GENERATE statement must be a (gloablly) static +expression. It cannot depend on a signal value or other non-static +value. + +This message will be an error with the -pedanticerrors argument. + +vcom Message # 1149: +The parameter value of the specified predefined attribute is outside +the range of the type of the prefix. +[DOC: IEEE Std 1076-1993 VHDL LRM - 14.1 Predefined attributes] + + +vcom Message # 1150: +The parameter value of the specified predefined attribute is an +illegal value; the attribute cannot return a legal value given +this parameter as input. +[DOC: IEEE Std 1076-1993 VHDL LRM - 14.1 Predefined attributes] + + +vcom Message # 1151: +The result of the specified predefined attribute is outside +the range of the type of the prefix. +[DOC: IEEE Std 1076-1993 VHDL LRM - 14.1 Predefined attributes] + + +vcom Message # 1152: +The index value must belong to both the corresponding index subtype of +the base array type and the corresponding index range of the constrained +array subtype. +The warning version of this message can be suppressed with the +vcom option -nowarn 14. + + +vcom Message # 1153: +The index value must belong to both the corresponding index subtype of +the base array type and the corresponding index range of the constrained +array subtype. + + +vcom Message # 1154: +The index value must belong to both the corresponding index subtype of +the base array type and the corresponding index range of the constrained +array subtype. +This is impossible when the range is a null range because no value can +belong to a null range. + + +vcom Message # 1155: +IEEE Std 1076-1993, 5.2.2 Default binding indication: +In a default binding indication, and in an explicit binding indication +that lacks a port map aspect, where the entity aspect (whether default +or explicit) implies a design entity that contains formal ports, a +default port map aspect is assumed within that binding indication. +The default port map aspect associates each local port (if any) of the +component declaration corresponding to the component instantiation with +a formal of the same simple name. Any unassociated formals are +associated with the actual designator OPEN. This means that these +formals are unconnected, which is legal in this situation. +When -lint is given, this message is produced to show the entity ports +that do not have a corresponding component port and are therefore left +unconnected. +This message is for informational purposes only. + + +vcom Message # 1156: +The result of the concatenation would have an array index range whose +right bound would not belong to the index subtype of the base type +of the array. + + +vcom Message # 1157: +The array index right bound does not belong to the index subtype of +the base type of the array at this index position. The length of the +array at this index position is too large to be represented by this +array type. + + +vcom Message # 1158: +Exponentiation is defined as repeated multiplication of the left +operand by itself for a number of times indicated by the absolute value +of the right operand. This operation has resulted in a number too +large in absolute value to be represented within the limits of the +implementation. + + +vcom Message # 1159: +Exponentiation with a negative exponent is allowed only for a left +operand of a floating point type. +[DOC: IEEE Std 1076-2002 VHDL LRM - 7.2.7 Miscellaneous operators] + + +vcom Message # 1160: +The evaluation of a qualified expression evaluates the operand and +checks that its value belongs to the subtype denoted by the type mark. +For array subtypes this means that at each position in the index +constraint, the index ranges must match. +This is technically an error and the simulator will produce a runtime +error. This error can be suppressed or downgraded, in which case a +subtype conversion will occur, just as though the VHDL 2008 rules were +in effect. +[DOC: IEEE Std 1076-1993 VHDL LRM - 7.3.4 Qualified expressions] + + +vcom Message # 1161: +IEEE Std 1076-1993, 2.1.1.2 Signal parameters, line 115: + If an actual signal is associated with a signal parameter of any mode, + and if the type of the formal is a scalar type, then it is an error if + the bounds and direction of the subtype denoted by the subtype + indication of the formal are not identical to the bounds and direction + of the subtype denoted by the subtype indication of the actual. + + +vcom Message # 1162: +VHDL 1993 and later allows an expression to be used as the actual for a +formal port as long as the port is of mode IN. +However, as a non-compliant exception to this rule, if the port is a +component port and it is of mode INOUT, we will allow an expression as +the actual as long as the entity port that the component port binds to +is of mode IN and the expression is globally static. + +This message will be an error with the -pedanticerrors argument. + +vcom Message # 1163: +A Verilog module having a port with a range that depends on a parameter +results in an equivalent VHDL entity (for the purposes of instantiating +Verilog in VHDL) with a port of an unconstrained array type. If the +port map of the VHDL instance of the Verilog module either has +individual associations or is an array aggregate or string literal +expression, then the array length and/or direction might not match +those of the elaborated Verilog port when the design is loaded, +possibly causing a bit-wise reversal of the actual value. For all the +array types supported at the VHDL-Verilog boundary, the Verilog port +will be assumed to have a direction of TO because the VHDL rules for +determining the index range of an unconstrained array formal +that is associated individually state that the direction is that of +the index subtype of the array, which is the predefined subtype NATURAL. +Use a component instantiation where the component port is of a +constrained array subtype with the same length and direction as the +corresponding elaborated Verilog module port's range. + + +vcom Message # 1164: +Impure function calls are not globally static expressions and +the actual of a port connection, if an expression, must be a +globally static expression. + + +vcom Message # 1165: +IEEE Std 1076-1993, 4.3.3.1 Object aliases, line 573: + If the subtype indication denotes a scalar subtype, then the object + is viewed as if it were of the subtype specified by the subtype + indication; moreover, it is an error if this subtype does not have + the same bounds and direction as the subtype denoted by the object + name. + + +vcom Message # 1166: +IEEE Std 1076-1993, 7.3.6 Allocators, line 545: + The only allowed form of constraint in the subtype indication of an + allocator is an index constraint. + + +vcom Message # 1167: +The index value must belong to both the corresponding index subtype of +the base array type and the corresponding index range of the constrained +array subtype. + + +vcom Message # 1168: +The index value must belong to both the index subtype of the base array +type and the index range of the constrained array subtype. + + +vcom Message # 1169: +The index constraint must provide a discrete range for each index of +the array type, and the type of each discrete range must be the same as +that of the corresponding index. +[DOC: IEEE Std 1076-1993 VHDL LRM - 3.2.1.1 Index constraints and discrete ranges] + + +vcom Message # 1170: +The index constraint must provide a discrete range for each index of +the array type, and the type of each discrete range must be the same as +that of the corresponding index. +[DOC: IEEE Std 1076-1993 VHDL LRM - 3.2.1.1 Index constraints and discrete ranges] + +This message will be an error with the -pedanticerrors argument. + +vcom Message # 1171: +The predefined attribute 'DRIVING requires that its prefix signal +have a driver present in the process in which it appears. +The predefined attribute 'DRIVING_VALUE requires that the value of +'DRIVING not be FALSE at the point of evaluation; this implies that +'DRIVING be evaluatable, hence it is an error if no drivers are present. +[DOC: IEEE Std 1076-1993 VHDL LRM - 14.1 Predefined attributes] + + +vcom Message # 1172: +The rules for multidimensional array aggregates require that each +element representing a subaggregate be either another aggregate, a +string literal, or a bit string literal. Because subarrays of +multidimensional array types have no type, there is no type with +which to resolve the element expression, and no implicit type conversion +can occur. QuestaSim will perform such a "type" conversion if possible +however. +Use the -pedanticerrors switch to enforce strict LRM compliance and make +this an error. +[DOC: IEEE Std 1076-1993 VHDL LRM - 7.3.2.2 Array aggregates] + + +vcom Message # 1173: +In a type conversion between array types, a check is made that any +constraint on the element subtype is the same for the operand array type +as for the target array type. +For an element subtype that is a scalar subtype, the bounds of +the range constraint must match those of the subtype of the operand. +For an element subtype that is an array subtype, the bounds of +each index range in the index constraint must match those of the +operand. +[DOC: IEEE Std 1076-1993 VHDL LRM - 7.3.5 Type conversions], line 490 + + +vcom Message # 1174: +IEEE Std 1076-1993, 7.3.2 Aggregates, line 392: + Each element of the value defined by an aggregate must be represented + once and only once in the aggregate. + + +vcom Message # 1175: +IEEE Std 1076-1993, 10.3 Visibility, line 143: + Within the specification of a subprogram, every declaration with the + same designator as the subprogram is hidden. Where hidden in this + manner, a declaration is visible neither by selection nor directly. + + +vcom Message # 1176: +The VHDL 1987 language requires that a subtype indication be present in +the declaration of an alias. +[DOC: IEEE Std 1076-1987 VHDL LRM - 4.3.4 Alias Declaration] + + +vcom Message # 1177: +VHDL syntax requires that the target type in a type conversion +expression be a type mark, which is just a simple type or subtype name +with no constraint (or resolution function either). + + +vcom Message # 1178: +VHDL syntax requires that a qualified expression type be a type_mark, +which is just a simple type or subtype name with no constraint (or +resolution function either). + + +vcom Message # 1179: +An individual association element whose formal designator is a slice +of the formal has a slice discrete range with a direction different +from the direction of the formal itself. +The slice is a null slice if the direction of the discrete range is not +the same as that of the object denoted by the prefix of the slice name. +[DOC: IEEE Std 1076-1987 VHDL LRM - 6.5 Slice names] +This was changed to an error in VHDL 1993, see message #1181. + + +vcom Message # 1180: +It is impossible to create a null slice (see warning message #1179) when +the bounds of the discrete range are identical. + + +vcom Message # 1181: +An individual association element whose formal designator is a slice +of the formal has a slice discrete range with a direction different +from the direction of the formal itself. +It is an error if the direction of the discrete range of a slice name +is not the same as that of the index range of the array denoted by the +prefix of the slice name. +[DOC: IEEE Std 1076-1993 VHDL LRM - 6.5 Slice names] + + +vcom Message # 1182: +The array index values given in the individual association elements +corresponding to the formal do not form a complete uninterrupted set +of values needed to form an association for every subelement of the +formal. +IEEE Std 1076-1993, 4.3.2.2 Association lists, line 506: + Furthermore, every scalar subelement of the explicitly declared + interface object must be associated exactly once with an actual (or + subelement thereof) in the same association list, and all such + associations must appear in a contiguous sequence within that + association list. + + +vcom Message # 1183: +A component instantiation label in the component specification of a +component configuration is a duplicate of such a label found in the +component specification of a configuration specification. +IEEE Std 1076-1993, 5.2 Configuration specification, line 146: + It is an error if the elaboration of a configuration specification + results in the association of binding information with a component + label that is already bound. + + +vcom Message # 1184: +The ALL instantiation list of the component specification of a +component configuration is associating binding information +with a component instance that has already been bound in a +configuration specification. +IEEE Std 1076-1993, 5.2 Configuration specification, line 146: + It is an error if the elaboration of a configuration specification + results in the association of binding information with a component + label that is already bound. + + +vcom Message # 1185: +A component instantiation label in the component specification of +a configuration specification is a duplicate of such a label found in a +preceding configuration specification. +IEEE Std 1076-1993, 5.2 Configuration specification, line 146: + It is an error if the elaboration of a configuration specification + results in the association of binding information with a component + label that is already bound. + + +vcom Message # 1186: +When the expression is of an array type, the length of the array must +be known at compile time. The simulator is less restrictive than the +LRM requires as long as the array length of the expression can be +determined in the compiler. +IEEE Std 1076-1993, 8.8 Case statement: + + If the expression is of a one-dimensional character array type, then + the expression must be one of the following: + -- The name of an object whose subtype is locally static + -- An indexed name whose prefix is one of the members of this list + and whose indexing expressions are locally static expressions + -- A slice name whose prefix is one of the members of this list and + whose discrete range is a locally static discrete range + -- A function call whose return type mark denotes a locally static + subtype + -- A qualified expression or type conversion whose type mark + denotes a locally static subtype + + It is an error if the element subtype of the one-dimensional character + array type is not a locally static subtype. + +This message will be an error with the -pedanticerrors argument. + +vcom Message # 1187: +It is an error if a composite type contains elements of file types or +protected types. +[DOC: IEEE Std 1076-2008 VHDL LRM - 5.3 Composite types] + + +vcom Message # 1188: +IEEE Std 1076-1993, 3.2.1.1 Index constraints and discrete ranges, line 410: + If the index ranges for an interface object or member of an interface + object are obtained from the corresponding association element, then + they are determined either by the actual part or by the formal part + of the association element, depending on the mode of the interface + object, as follows: +IEEE Std 1076-1993, 3.2.1.1 Index constraints and discrete ranges, line 419: + For an interface object or member of an interface object whose mode + is OUT, BUFFER, INOUT, or LINKAGE, if the formal part includes a + conversion function or a type conversion, then the parameter subtype + of that function or the type mark of the type conversion must be a + constrained array subtype, and the index ranges are obtained from + this constrained subtype; otherwise, the index ranges are obtained + from the object denoted by the actual designator. + + +vcom Message # 1189: +IEEE Std 1076-1993, 3.2.1.1 Index constraints and discrete ranges, line 410: + If the index ranges for an interface object or member of an interface + object are obtained from the corresponding association element, then + they are determined either by the actual part or by the formal part + of the association element, depending on the mode of the interface + object, as follows: +IEEE Std 1076-1993, 3.2.1.1 Index constraints and discrete ranges, line 419: + For an interface object or member of an interface object whose mode + is OUT, BUFFER, INOUT, or LINKAGE, if the formal part includes a + conversion function or a type conversion, then the parameter subtype + of that function or the type mark of the type conversion must be a + constrained array subtype, and the index ranges are obtained from + this constrained subtype; otherwise, the index ranges are obtained + from the object denoted by the actual designator. + + +vcom Message # 1190: +IEEE Std 1076-1993, 3.2.1.1 Index constraints and discrete ranges, line 410: + If the index ranges for an interface object or member of an interface + object are obtained from the corresponding association element, then + they are determined either by the actual part or by the formal part + of the association element, depending on the mode of the interface + object, as follows: +IEEE Std 1076-1993, 3.2.1.1 Index constraints and discrete ranges, line 414: + For an interface object or member of an interface object whose mode + is IN, INOUT, or LINKAGE, if the actual part includes a conversion + function or a type conversion, then the result type of that function + or the type mark of the type conversion must be a constrained array + subtype, and the index ranges are obtained from this constrained + subtype; otherwise, the index ranges are obtained from the object + denoted by the actual designator. + +This message will be an error with the -pedanticerrors argument. + +vcom Message # 1191: +IEEE Std 1076-1993, 3.2.1.1 Index constraints and discrete ranges, line 410: + If the index ranges for an interface object or member of an interface + object are obtained from the corresponding association element, then + they are determined either by the actual part or by the formal part + of the association element, depending on the mode of the interface + object, as follows: +IEEE Std 1076-1993, 3.2.1.1 Index constraints and discrete ranges, line 414: + For an interface object or member of an interface object whose mode + is IN, INOUT, or LINKAGE, if the actual part includes a conversion + function or a type conversion, then the result type of that function + or the type mark of the type conversion must be a constrained array + subtype, and the index ranges are obtained from this constrained + subtype; otherwise, the index ranges are obtained from the object + denoted by the actual designator. + +This message will be an error with the -pedanticerrors argument. + +vcom Message # 1192: +The number of array elements present in the array aggregate does not +equal the array length at the corresponding index position. This is a +matching element test that has failed (see [7.2.2 Relational operators] +in the IEEE Std 1076-2002 LRM). + + +vcom Message # 1193: +The choice values given in the individual association elements of the +formal correspond to a different number of array elements than the type +of the formal has at that index position. +IEEE Std 1076-1993, 4.3.2.2 Association lists, line 506: + Furthermore, every scalar subelement of the explicitly declared + interface object must be associated exactly once with an actual (or + subelement thereof) in the same association list, and all such + associations must appear in a contiguous sequence within that + association list. + + +vcom Message # 1194: +A FILE declaration was written using VHDL 1987 syntax, while the +language version being used is a newer standard (1993/2002/2008). +The FILE declaration will be processed according to the 1987 language +rules. + + +vcom Message # 1195: +An expanded name that could not be completely resolved was used. The +suffix does not name something that exists within the scope of the +prefix specified. + + +vcom Message # 1196: +The prefix of the selected name could not be resolved as the name of a +visible named entity. + + +vcom Message # 1197: +The syntax requires a component name. The name given does not denote a +component declaration. + + +vcom Message # 1198: +The name is the name of a method of a protected type. A method of +a protected type is visible only when used as the suffix of a selected +name whose prefix denotes a VARIABLE object of that protected type. + + +vcom Message # 1200: +The value returned via a RETURN statement in a function must belong to +the return type mark of the function. When the function return type +mark denotes a constrained array subtype, not only must the index range +at every index position of the return value have the same bounds as the +corresponding index range of this subtype, the direction of each index +range must match that of the corresponding range of this subtype. +Use the -pedanticerrors switch for strict VHDL compliance to make this +an error; otherwise, an implicit subtype conversion to the constrained +array subtype denoted by the function return type mark will be done. +[DOC: IEEE Std 1076-1993 VHDL LRM - 8.12 Return statement] + +This message will be an error with the -pedanticerrors argument. + +vcom Message # 1201: +An access value belongs to a corresponding subtype of an access type +either if the access value is the NULL value or if the value of the +designated object satisfies the constraint. +[DOC: IEEE Std 1076-1993 VHDL LRM - 3.3 Access types] + +A scalar value must belong to the designated subtype of the access type. +Example: + type acc is access integer range 1 to 10; + -- Objects designated by type "acc" must have a value that satisfies + -- 1 <= value <= 10. +A composite value that includes array subelements must be such that all +array subelements have index ranges that are identical in bounds and +direction to the index ranges implied by the union of the constraint +(if any) present in an access subtype definition and the constraint (if +any) present in the subtype indication used in the access type +definition. +Example: + type arr is array(natural range <>) of bit_vector; + type acc is access arr(OPEN)(1 to 3); + subtype sub is acc(4 to 5); + -- Objects designated by type "acc" can have any index range of + -- either direction as long as it belongs to the range of NATURAL; + -- the BIT_VECTOR subelements must have an index range of (1 to 3). + -- Objects designated by subtype "sub" must have have an index range + -- exactly equal to (4 to 5), and the BIT_VECTOR subelements must all + -- have an index range equal to (1 to 3). + + +vcom Message # 1202: +VHDL 1987 syntax does not allow an instantiated unit kind to be +specified in a component instantiation statement. Remove the reserved +word or use VHDL 1993 or later (vcom options -93, -2002, etc.). + +This message will be an error with the -pedanticerrors argument. + +vcom Message # 1203: +The terminating string literal string bracket character was not found. +A string literal is formed by a sequence of graphic characters +(possibly none) enclosed between two quotation marks (") used as +string brackets. The quotation marks used as string brackets at both +ends of a string literal can be replaced by percent signs (%) provided +that both string brackets are replaced and that the enclosed sequence +of characters contains no quotation marks. + + +vcom Message # 1204: +The terminating bit string literal bit string bracket character was not +found. A bit string literal is formed by a sequence of extended digits +(possibly none) enclosed between two quotations (") used as bit string +brackets, preceded by a base specifier. The quotation marks used as +bit string brackets at both ends of a bit string literal can be +replaced by percent signs (%) provided that both bit string brackets +are replaced. + + +vcom Message # 1205: +The character found in a bit string literal is not an extended digit. +Or, a quotation mark is not legal in a string literal for which the +string brackets are the replacement character '%'. + + +vcom Message # 1206: +The character found in a bit string literal is not an extended digit. + + +vcom Message # 1207: +[13.2 Lexical elements, separators, and delimiters], line 130: + At least one separator is required between an identifier or an + abstract literal and an adjacent identifier or abstract literal. + +This message will be an error with the -pedanticerrors argument. + +vcom Message # 1208: +If a range constraint is used in a subtype indication, the type of the +expressions (likewise, of the bounds of a range attribute) must be the +same as the base type of the type mark of the subtype indication. +[DOC: IEEE Std 1076-1993 VHDL LRM - 3.1 Scalar types] + +This message will be an error with the -pedanticerrors argument. + +vcom Message # 1209: +The index constraint must provide a discrete range for each index of +the array type, and the type of each discrete range must be the same as +that of the corresponding index. +[DOC: IEEE Std 1076-1993 VHDL LRM - 3.2.1.1 Index constraints and discrete ranges] + +This message will be an error with the -pedanticerrors argument. + +vcom Message # 1210: +The index constraint must provide a discrete range for each index of +the array type, and the type of each discrete range must be the same as +that of the corresponding index. +[DOC: IEEE Std 1076-1993 VHDL LRM - 3.2.1.1 Index constraints and discrete ranges] + +This message will be an error with the -pedanticerrors argument. + +vcom Message # 1211: +The entity class "property" is available only starting with the 2008 +version of the language. +Use VHDL 2008 or later (vcom option -2008). + + +vcom Message # 1212: +The entity class "sequence" is available only starting with the 2008 +version of the language. +Use VHDL 2008 or later (vcom option -2008). + + +vcom Message # 1213: +An entity designator given in the attribute specification does not +denote any named entity to decorate with the attribute value. +Each entity designator in an attribute specification must denote at +least one named entity. If a signature appears in the entity designator, +then exactly one named entity must be denoted. +IEEE Std 1076-1993, 5.1 Attribute specification, line 54: + The entity tag of an entity designator containing a signature must + denote one or more subprograms or enumeration literals. In this case, + the signature must match (see 2.3.2) the parameter and result type + profile of exactly one subprogram or enumeration literal in the + current declarative part. +If a signature is present, QuestaSim permits the entity designator to +denote no named entity (for backwards compatibility); however, in this +case the attribute specification does not decorate any named entity. + +This message will be an error with the -pedanticerrors argument. + +vcom Message # 1214: +An entity designator given in the attribute specification does not +denote any named entity of the specified entity class. +Each entity designator in an attribute specification must denote at +least one named entity in the specified entity class. +IEEE Std 1076-1993, 5.1 Attribute specification, line 37: + If a list of entity designators is supplied, then the attribute + specification applies to the named entities denoted by those + designators. It is an error if the class of those names is not the + same as that denoted by the entity class. + + +vcom Message # 1215: +An entity designator given in the attribute specification does not +denote any named entity of the specified entity class. +Each entity designator in an attribute specification must denote at +least one named entity in the specified entity class. +IEEE Std 1076-1993, 5.1 Attribute specification, line 37: + If a list of entity designators is supplied, then the attribute + specification applies to the named entities denoted by those + designators. It is an error if the class of those names is not the + same as that denoted by the entity class. +QuestaSim will allow entity classes "function" and "procedure" to be +considered to be equivalent for backwards compatibility with non-compliant +behavior found in prior releases. + + +vcom Message # 1216: +The reserved word SUBTYPE cannot appear as the attribute designator in +an attribute name prior to VHDL 2008. + + +vcom Message # 1217: +The syntax for a configuration declaration requires that a block +configuration appear immediately within the declaration, after the +configuration declarative part (which comprises zero or more +configuration declarative items). +IEEE Std 1076-1993, 1.3 Configuration declarations, line 292 + + +vcom Message # 1218: +The syntax requires a component name. The name given does not denote a +component declaration. + + +vcom Message # 1219: +The syntax requires a component name. The name given may be appropriate +only for the syntax legal after the reserved word ENTITY in either an +instantiated unit (see 9.6 Component instantiation statements) or an +entity aspect (see 5.2.1.1 Entity aspect). +[DOC: IEEE Std 1076-1993 VHDL LRM] + + +vcom Message # 1220: +An integer divide, modulo, or remainder operation has a right operand +of zero, which is causing a divide by zero error. + + +vcom Message # 1221: +A floating point divide has a right operand of zero, or a floating point +exponentiation has a left operand of zero and a right operand of a +negative value, which is causing a divide by zero condition. + + +vcom Message # 1222: +The expression did not satisfy the requirements for a CASE expression +or a selected signal assignment expression of an array type. +IEEE Std 1076-1993, 8.8 Case statement: + + If the expression is of a one-dimensional character array type, then + the expression must be one of the following: + -- The name of an object whose subtype is locally static + -- An indexed name whose prefix is one of the members of this list + and whose indexing expressions are locally static expressions + -- A slice name whose prefix is one of the members of this list and + whose discrete range is a locally static discrete range + -- A function call whose return type mark denotes a locally static + subtype + -- A qualified expression or type conversion whose type mark + denotes a locally static subtype + + It is an error if the element subtype of the one-dimensional character + array type is not a locally static subtype. + +This message will be an error with the -pedanticerrors argument. + +vcom Message # 1223: +The expression did not satisfy the requirements for a CASE expression +or a selected signal assignment expression of an array type. +IEEE Std 1076-1993, 8.8 Case statement: + + If the expression is of a one-dimensional character array type, then + the expression must be one of the following: + -- The name of an object whose subtype is locally static + -- An indexed name whose prefix is one of the members of this list + and whose indexing expressions are locally static expressions + -- A slice name whose prefix is one of the members of this list and + whose discrete range is a locally static discrete range + -- A function call whose return type mark denotes a locally static + subtype + -- A qualified expression or type conversion whose type mark + denotes a locally static subtype + + It is an error if the element subtype of the one-dimensional character + array type is not a locally static subtype. + +This message will be an error with the -pedanticerrors argument. + +vcom Message # 1224: +The expression did not satisfy the requirements for a CASE expression +or a selected signal assignment expression of an array type. +IEEE Std 1076-1993, 8.8 Case statement: + + If the expression is of a one-dimensional character array type, then + the expression must be one of the following: + -- The name of an object whose subtype is locally static + -- An indexed name whose prefix is one of the members of this list + and whose indexing expressions are locally static expressions + -- A slice name whose prefix is one of the members of this list and + whose discrete range is a locally static discrete range + -- A function call whose return type mark denotes a locally static + subtype + -- A qualified expression or type conversion whose type mark + denotes a locally static subtype + + It is an error if the element subtype of the one-dimensional character + array type is not a locally static subtype. + +This message will be an error with the -pedanticerrors argument. + +vcom Message # 1225: +IEEE Std 1076-1993, 2.1.1.2 Signal parameter: + + A formal signal parameter is a guarded signal if and only if + it is associated with an actual signal that is a guarded signal. + It is an error if the declaration of a formal signal parameter + includes the reserved word BUS. +(The grammar also disallows REGISTER.) + + +vcom Message # 1226: +It is an error if a wait statement appears in an explicit process +statement that includes a sensitivity list or in a procedure that +has a parent that is such a process statement. +[DOC: IEEE Std 1076-1993 VHDL LRM - 8.1 Wait statement] + + +vcom Message # 1227: +[DOC: IEEE Std 1076-1987 8.2 Assertion statements] +The only place the reserved word REPORT is found in the syntax of +VHDL 1987 is within the assertion statement. + +This message will be an error with the -pedanticerrors argument. + +vcom Message # 1228: +IEEE Std 1076-5.2.1.1: +In an entity aspect used in a binding indication in a configuration +specification or component configuration, when that entity aspect +contains an architecture identifier, the architecture body so +identified is not required to exist at analysis time unless the binding +indication is part of a component configuration that has explicit block +configurations or explicit component configurations. +This warning message is given to remind the user that the architecture +needs to exist at the time the design is loaded. +Note that this warning is normally issued in conjunction with the -lint +and/or the -bindAtCompile option. To receive this warning as a matter +of course, change the severity of this message via the '-warning 1228' +options or make a similar change to the [msg_system] section of the +modelsim.ini file. +Note that for mixed-language designs in which the entity aspect +identifies a non-VHDL design unit, the architecture name (when present) +is ignored as long as there is no inner block configuration (such an +inner block configuration causes an error because non-VHDL blocks cannot +be configured from VHDL configurations). + + +vcom Message # 1229: +The function or procedure is making recursive calls to itself. +Make sure that there is a terminating case to avoid infinite recursion. + + +vcom Message # 1236: +Shared variables were introduced into the language in the VHDL 1993 LRM, +before the introduction of protected types, which occurred in VHDL 2002. +The VHDL 2002 LRM also introduced the requirement that shared variables +be of a protected type so that certain semantics regarding the use of +shared variables could be guaranteed. In the interest of allowing +VHDL 1993-compliant code to be compiled using the VHDL 2002 rules, this +requirement for VHDL 2002 has by default been relaxed (producing a +warning) with the caveat that the shared variable semantics described by +the VHDL 2002 LRM will not necessarily be enforced. Instead, the +VHDL 1993 behavior will be in effect for such non-protected type shared +variables. +This message can be suppressed or have its severity level changed. +IEEE Std 1076-2002, 4.3.1.3 Variable declarations: + + The base type of the subtype indication of a shared variable + declaration must be a protected type. + +This message will be an error with the -pedanticerrors argument. + +vcom Message # 1239: +An individual association element whose formal designator is a slice +of the formal has a slice discrete range with a direction different +from the would-be direction of the formal itself. +It is an error (null slice in VHDL 1987) if the direction of the +discrete range of a slice name is not the same as that of the index +range of the array denoted by the prefix of the slice name. + +However, in the case where the formal is of an unconstrained array +type (and thus the direction would normally come from the direction of +the index subtype of this base array type), the compiler will use the +direction of the first formal slice name that appears in the individual +association elements in the association list (all slices of this formal +must therefore have the same direction); this is non-compliant +behavior. +[DOC: IEEE Std 1076-1993 VHDL LRM - 6.5 Slice names] + +This message will be an error with the -pedanticerrors argument. + +vcom Message # 1244: +An individual association element whose formal designator is a slice +of the formal has a slice discrete range with a direction different +from a prior slice name of the same formal. At least one of these +slice names is an error (VHDL 1993) or unsupported (VHDL 1987). + + +vcom Message # 1245: +The package STD.TEXTIO is an integral part of the language and as such +does not have a package body. Its subprograms achieve their effect +through an implementation that is an integral part of the simulator, +and thus there is no VHDL-source package body to use as requested by the +"-noaccel textio" option. + + +vcom Message # 1246: +The specified range is a null range and therefore contains no values. +This occurs when the direction is TO and LEFT > RIGHT, or when the +direction is DOWNTO and LEFT < RIGHT. + + +vcom Message # 1247: +The specified range is a null range and therefore contains no values. +This occurs when the direction is TO and LEFT > RIGHT, or when the +direction is DOWNTO and LEFT < RIGHT. + + +vcom Message # 1248: +The specified range is a null range and therefore contains no values. +This occurs when the direction is TO and LEFT > RIGHT, or when the +direction is DOWNTO and LEFT < RIGHT. + + +vcom Message # 1249: +The named package is an integral part of the language and as such does +not have a package body. Its subprograms achieve their effect through +an implementation that is an integral part of the simulator, and thus +there is no VHDL-source package body to use as requested by the +"-noaccel " option. + + +vcom Message # 1250: +The default binding for this component instantiation cannot be used. +The preceding compiler warning message contains the reason. If the +default binding is used, an elaboration error will be produced, and the +design will not load. This warning can be ignored if the component +instance will be bound via an explicit binding indication as part of a +component configuration in an applicable configuration declaration. +This message can be suppressed with the vcom option -nowarn 1. + + +vcom Message # 1251: +IEEE Std 1076-1993, 5.2.2 Default binding indication: +In a default binding indication, and in an explicit binding indication +that lacks a generic map aspect, where the entity aspect (whether +default or explicit) implies a design entity that contains formal +generics, a default generic map aspect is assumed within that binding +indication. The default generic map aspect associates each local +generic (if any) of the component declaration corresponding to the +component instantiation with a formal of the same simple name. Any +unassociated formals are associated with the actual designator OPEN. +This means that these formals are unconnected, which is not legal in +this situation because of the following requirement: +IEEE Std 1076-1993, 1.1.1.1 Generics, line 74: + It is an error if no actual is specified for a given formal generic + and no default expression is present in the corresponding interface + element. + +This message is only a warning because the simulator option "-g" can be +used to provide a value to otherwise unconnected generic. + + +vcom Message # 1252: +IEEE Std 1076-1993, 5.2.2 Default binding indication: +In a default binding indication, and in an explicit binding indication +that lacks a generic map aspect, where the entity aspect (whether +default or explicit) implies a design entity that contains formal +generics, a default generic map aspect is assumed within that binding +indication. The default generic map aspect associates each local +generic (if any) of the component declaration corresponding to the +component instantiation with a formal of the same simple name. Any +unassociated formals are associated with the actual designator OPEN. +This means that these formals are unconnected, which is legal in this +situation. When -lint is given, this message is produced to show the +entity generics that do not have a corresponding component generic and +are therefore left unconnected. +This message is for informational purposes only. + + +vcom Message # 1253: +The default binding for the component instantiation statement could not +created because no entity with the same name as the component could +not be found. + + +vcom Message # 1254: +The resolution function(s) implied by the subtype indication present in +the object alias declaration will be ignored. The declaration of the +denoted object already contains or implies the applicable resolution +function(s). This warning is issued only for SIGNAL aliases because +resolution applies only to signals. + + +vcom Message # 1255: +IEEE Std 1076-2008 6.3 Subtype declarations. + If a resolution indication is in the form that contains an element + resolution that is an array element resolution, then the subtype + corresponding to the resolution indication shall be an array subtype. + + +vcom Message # 1256: +IEEE Std 1076-2008 6.3 Subtype declarations. + If a resolution indication is in the form that contains an element + resolution that is a record resolution, then the subtype corresponding + to the resolution indication shall be a record subtype. + + +vcom Message # 1257: +IEEE Std 1076-1993 12.3.1.2 Type declarations: + Elaboration of a protected type body has no effect other than to + establish that the body, from then on, can be used during the + elaboration of objects of the protected type. +In particular (but not exclusively), this rule prevents a package +declaration from containing both a protected type declaration and a +(shared) variable declaration of that type; this is because a protected +type body cannot be declared in a package declaration. +Use the "-allowProtectedBeforeBody" compiler switch to disable this +check; however, indeterminate results are possible if this rule is +violated. + + +vcom Message # 1258: +A port that is not of mode IN and that is of an unconstrained array +type must be associated with an actual; the index range(s) of the +actual are used to define those of the port. When the port has a +default expression in its declaration, the array length of the default +expression must match that of the actual at each index position in the +array type. This is because the default expression is used to define +the initial driving value of the port. + + +vcom Message # 1259: +A port that is not of mode IN and that is of an unconstrained array +type must be associated with an actual; the index range(s) of the +actual are used to define those of the port. When the port has a +default expression in its declaration, the array length of the default +expression must match that of the actual at each index position in the +array type. This is because the default expression is used to define +the initial driving value of the port. + + +vcom Message # 1260: +IEEE Std 1076-1993 [6.3 Selected names], line 90: + For a selected name that is used to denote a record element, the + suffix must be a simple name denoting an element of a record object or + value. The prefix must be appropriate for the type of this object or + value. +The rules for selected names do not describe a scenario in which the +prefix is a record type mark; note the use of "object or value" above. +For historical reasons, QuestaSim supports a selected name (which will be +treated as an expanded name) that represents the declaration of an +element of a record type. + +This message will be an error with the -pedanticerrors argument. + +vcom Message # 1261: +The design has referenced a declaration which is not defined for the +language version currently in effect. Use a different language version. + + +vcom Message # 1262: +IEEE Std 1076-2008 6.3 Subtype declarations. +In language versions before VHDL 2008, only a resolution function name +can be used to specify a resolution function; that is, the VHDL 2008 +element resolution syntax is not available. + + +vcom Message # 1263: +The configuration specification or component configuration does not +apply to any component instantiation statements. Only those component +instantiation statements whose labels (implicitly) appear immediately in +a given declarative part are considered to be associated with a +configuration specification or component configuration that appears in +that same declarative part. +[DOC: IEEE Std 1076-1993 VHDL LRM - 5.2 Configuration specifications] +[DOC: IEEE Std 1076-1993 VHDL LRM - 1.3.2 Component configuration] + + +vcom Message # 1270: +The default binding for the component instantiation statement has +error(s) because not all the component ports have counterparts on +the entity to which the component instantiation is being bound. + + +vcom Message # 1271: +The default binding for the component instantiation statement has +error(s) because not all the component generics have counterparts on +the entity to which the component instantiation is being bound. + + +vcom Message # 1272: +The actual array length did not match the expected array length. + + +vcom Message # 1273: +The actual array is multidimensional, and the length of it at the index +position specified does not match the expected array length. + + +vcom Message # 1274: +It is an error if a wait statement appears in a function subprogram +or in a procedure that has a parent that is a function subprogram. +[DOC: IEEE Std 1076-1993 VHDL LRM - 8.1 Wait statement] + + +vcom Message # 1275: +For those binary operators defined for one-dimensional array types, the +operands must be arrays of the same length. +[DOC: IEEE Std 1076-1993 VHDL LRM - 7.2.1 Logical operators] +Also, many binary operators defined in package ieee.std_logic_1164 have +this requirement. + + +vcom Message # 1276: +See the Reference Manual for details on usage. +Option "-mixedsvvh" has not been used correctly. Correct usage is + -mixedsvvh [] + b => generate equivalent 2-state bit type + l => generate equivalent 4-state logic type + r => generate equivalent 4-state reg type + i => will ignore the range of vhdl integer & real types + and convert all integer types to int + NULL => default VHDL-SV type conversion + + +vcom Message # 1277: +For specifics consult the QuestaSim User's Manual on mixed language simulation. + + +vcom Message # 1278: +For specifics consult the QuestaSim User's Manual on mixed language simulation. + + +vcom Message # 1279: +The package being compiled with -mixedsvvh option is dependent on other package(s). +All packages on which this package has a dependency must be compiled +with the -mixedsvvh option before compiling this package. +For specifics refer to the QuestaSim User's Manual on mixed language simulation. + + +vcom Message # 1280: +For specifics refer to the QuestaSim User's Manual on mixed language simulation. + + +vcom Message # 1281: +For specifics refer to the QuestaSim User's Manual on mixed language simulation. + + +vcom Message # 1282: +The rules for a pure function subprogram require that any signal or +variable (or any member of thereof) referenced in it be declared in +the declarative region formed by the function. Furthermore, a pure +function cannot contain a reference to a FILE object. +[DOC: IEEE Std 1076-1993 VHDL LRM - 2.2 Subprogram bodies] + + +vcom Message # 1283: +The rules for a pure function subprogram require that any signal or +variable (or any member of thereof) referenced in it be declared in +the declarative region formed by the function. Furthermore, a pure +function cannot contain a reference to a FILE object. +[DOC: IEEE Std 1076-1993 VHDL LRM - 2.2 Subprogram bodies] + +This message will be an error with the -pedanticerrors argument. + +vcom Message # 1284: +The subprogram being called from a pure function has a reference to a +FILE object. +A pure function cannot be the parent of an impure function; nor can it +be the parent of a procedure that references a signal or variable (or +member of such) that has not been declared within the declarative region +formed by the pure function or the declarative region formed by the +procedure. Furthermore, a procedure whose parent is a pure function +cannot contain a reference to a FILE object or to a shared variable. +[DOC: IEEE Std 1076-1993 VHDL LRM - 2.2 Subprogram bodies] + +This message will be an error with the -pedanticerrors argument. + +vcom Message # 1285: +A pure function cannot be the parent of an impure function; nor can it +be the parent of a procedure that references a signal or variable (or +member of such) that has not been declared within the declarative region +formed by the pure function or the declarative region formed by the +procedure. Furthermore, a procedure whose parent is a pure function +cannot contain a reference to a FILE object or to a shared variable. +[DOC: IEEE Std 1076-1993 VHDL LRM - 2.2 Subprogram bodies] + +This message will be an error with the -pedanticerrors argument. + +vcom Message # 1286: +It is an error if, in a given block configuration, more than one +configuration item is defined for the same block or component instance. +[DOC: IEEE Std 1076-2002 VHDL LRM - 1.3.1 Block configuration] + +This message will be an error with the -pedanticerrors argument. + +vcom Message # 1287: +The name of the generic did not follow the required naming convention. +One or more required (underscore-separated) tokens were not found. +Use the -pedanticerrors switch for strict VHDL compliance to make this +an error. + + +vcom Message # 1288: +The port name(s) extracted from the timing generic port specification +did not correspond to ports on the enclosing entity. +This message is for informational purposes only. + + +vcom Message # 1289: +A +acc or +floatgenerics switch, with an instance path specified, has +been applied to a FOR...GENERATE statement that cannot be unrolled. +Therefore, all iterations of the statement satisfy the instance path. + + +vcom Message # 1290: +The value of a signal is not defined until after the design hierarchy +has been elaborated. Use of the signal name in a declarative item is +prohibited because the value is undefined until the entire design has +been elaborated. +[DOC: IEEE Std 1076-1993 VHDL LRM - 12.3 Elaboration of a declarative part] + + +vcom Message # 1291: +The type of a formal port or parameter must be compatible with the type +of the actual expression associated with it. These types are not +compatible. A conversion function or a type conversion may be needed to +allow the association. + + +vcom Message # 1292: +The slice's discrete range was specified with a particular direction, +but the direction of the prefix of the slice name is not known. Unless +the directions match in all situations, a simulation error will occur. + + +vcom Message # 1293: +The value of the index of the indexed name may not necessarily belong to +the index range of the prefix (at a particular index position). This +message occurs when a known index value is used to index into an array +of an unconstrained array type. + + +vcom Message # 1294: +Two declarations that occur immediately within the same declarative +region must not be homographs, unless exactly one of them is the +declaration of a predefined operation. +Each of two declarations is said to be a homograph of the other if both +declarations have the same identifier, operator symbol, or character +literal, and if overloading is allowed for at most one of the two. +If overloading is allowed for both declarations, then each of the two is +a homograph of the other if they have the same identifier, operator +symbol, or character literal, as well as the same parameter and result +type profile (see 3.1.1). Overloading is defined only for subprograms +(including those those whose designator is an operator symbol) and +enumeration literals (including character literals). +[DOC: IEEE Std 1076-1993 VHDL LRM - 10.3 Visibility] + + +vcom Message # 1295: +Two declarations that occur immediately within the same declarative +region must not be homographs, unless exactly one of them is the +declaration of a predefined operation. +Each of two declarations is said to be a homograph of the other if both +declarations have the same identifier, operator symbol, or character +literal, and if overloading is allowed for at most one of the two. +If overloading is allowed for both declarations, then each of the two is +a homograph of the other if they have the same identifier, operator +symbol, or character literal, as well as the same parameter and result +type profile (see 3.1.1). Overloading is defined only for subprograms +(including those those whose designator is an operator symbol) and +enumeration literals (including character literals). +[DOC: IEEE Std 1076-1993 VHDL LRM - 10.3 Visibility] + + +vcom Message # 1296: +The identifiers and character literals listed by an enumeration type +must be distinct within the enumeration type definition. +[DOC: IEEE Std 1076-1993 VHDL LRM - 3.1.1 Enumeration types] + + +vcom Message # 1297: +Two declarations that occur immediately within the same declarative +region must not be homographs, unless exactly one of them is the +declaration of a predefined operation. +Each of two declarations is said to be a homograph of the other if both +declarations have the same identifier, operator symbol, or character +literal, and if overloading is allowed for at most one of the two. +If overloading is allowed for both declarations, then each of the two is +a homograph of the other if they have the same identifier, operator +symbol, or character literal, as well as the same parameter and result +type profile (see 3.1.1). Overloading is defined only for subprograms +(including those those whose designator is an operator symbol) and +enumeration literals (including character literals). +[DOC: IEEE Std 1076-1993 VHDL LRM - 10.3 Visibility] + + +vcom Message # 1298: +An OTHERS choice in a CASE statement can appear only as the only choice +in the last case statement alternative. +An OTHERS choice in a selected signal assignment statement can appear +only as the only choice in the last of the selected waveforms. +An OTHERS choice in a selected variable assignment statement can appear +only as the only choice in the last of the selected expressions. +An OTHERS choice in a case generate statement can appear only as the +only choice in the last case generate alternative. +[DOC: IEEE Std 1076-1993 VHDL LRM - 8.8 Case statement] +[DOC: IEEE Std 1076-1993 VHDL LRM - 9.5.2 Selected signal assignments] +[DOC: IEEE Std 1076-2008 VHDL LRM - 10.6.4 Selected variable assignments] +[DOC: IEEE Std 1076-2008 VHDL LRM - 11.8 Generate statements] + + +vcom Message # 1299: +An OTHERS choice in a CASE statement can appear only as the only choice +in the last case statement alternative. +An OTHERS choice in a selected signal assignment statement can appear +only as the only choice in the last of the selected waveforms. +An OTHERS choice in a selected variable assignment statement can appear +only as the only choice in the last of the selected expressions. +In this case, since the OTHERS choice is the last choice over all the +choices, we allow this non-compliant behavior. +Use the -pedanticerrors switch for strict VHDL compliance to make this +an error. +[DOC: IEEE Std 1076-1993 VHDL LRM - 8.8 Case statement] +[DOC: IEEE Std 1076-1993 VHDL LRM - 9.5.2 Selected signal assignments] +[DOC: IEEE Std 1076-2008 VHDL LRM - 10.6.4 Selected variable assignments] + +This message will be an error with the -pedanticerrors argument. + +vcom Message # 1300: +Only object classes of VARIABLE, CONSTANT, and SIGNAL are valid for +external names. +[DOC: IEEE Std 1076-2008 VHDL LRM - 8.7 External names] + + +vcom Message # 1301: +The syntax for an external name does not allow a slice name to be present. +The pathname in an external name must refer to a single object, so a +slice of a FOR GENERATE statement label is not legal. +[DOC: IEEE Std 1076-2008 VHDL LRM - 8.7 External names] + + +vcom Message # 1302: +An indexed name in the pathname of an external name is allowed only when +the prefix is a FOR GENERATE label and therefore only when there is +exactly one index expression present. +[DOC: IEEE Std 1076-2008 VHDL LRM - 8.7 External names] + + +vcom Message # 1303: +Only a globally static expression is allowed as the index expression +in an indexed name in the pathname of an external name. +[DOC: IEEE Std 1076-2008 VHDL LRM - 8.7 External names] + + +vcom Message # 1304: +A package pathname must denote an object declared in a package. +Either the pathname does not denote a package, or the named object does +not exist in the package. +[DOC: IEEE Std 1076-2008 VHDL LRM - 8.7 External names] + + +vcom Message # 1305: +The pathname prefix ".^." is a non-standard extension to VHDL pathnames +to allow VHDL in mixed language designs to reference other top level design +roots. Use of this construct is non-portable. +[DOC: IEEE Std 1076-2008 VHDL LRM - 8.7 External names] + +This message will be an error with the -pedanticerrors argument. + +vcom Message # 1306: +The package referred to in the external name package pathname is not a package. +[DOC: IEEE Std 1076-2008 VHDL LRM - 8.7 External names] + + +vcom Message # 1307: +An external name must denote the entire target object. When forming a +slice name or indexed name of an external object, the discrete range or +index expression(s) must appear after the closing ">>" which +terminates the external name that denotes that object. +[DOC: IEEE Std 1076-2008 VHDL LRM - 8.7 External names] + + +vcom Message # 1308: +The specified input Verilog port is not connected from the VHDL +instantiation of the Verilog module. + + +vcom Message # 1309: +When an external name is evaluated during elaboration, the target object +of the external name must already have been elaborated. +A common error is to declare an alias declaration that denotes an +external name that denotes an object in a design hierarchy (i.e., a +component instantiation statement) that appears in the statement part +corresponding to the declarative region where the alias declaration +appears. For an external name that has a relative pathname, this can be +detected at compile time; other cases such as an absolute path or a path +that contains an up-scope reference cannot be detected until run time. +[DOC: IEEE Std 1076-2008 VHDL LRM - 8.7 External names] +[DOC: IEEE Std 1076-2008 VHDL LRM - 14.4.1 Elaboration of declarative part, General] + + +vcom Message # 1310: +A resolution function must be a pure function. +[DOC: IEEE Std 1076-2008 VHDL LRM - 4.6 Resolution functions] + +This message will be an error with the -pedanticerrors argument. + +vcom Message # 1311: +The total amount of memory any one array can occupy is limited to +2147483647 bytes. + + +vcom Message # 1312: +A selected name with a given suffix should refer either to an element of +an object or value of a record type, or to a method of a protected type. +Either the suffix name is incorrect or the expression is not of the +expected type. + + +vcom Message # 1313: +The indicated protect directive can be specified only once in a given +encryption envelope. +[DOC: IEEE Std 1076-2008 VHDL LRM - 24.1.4 Encryption envelopes] + + +vcom Message # 1315: +An encrypt key specification implies a randomly generated data key. +Therefore, the presence of one or more encrypt key specifications means +that an encrypt data specification, if present, can contain only the +"data_method" keyword. +[DOC: IEEE Std 1076-2008 VHDL LRM - 24.1.4.3 Encrypt data specifications] + + +vcom Message # 1316: +When an encrypt key specification is given in an encryption envelope, a +data method must have been supplied. If no data method was given, a +default method will be chosen by the encryption tool. +[DOC: IEEE Std 1076-2008 VHDL LRM - 24.1.4.3 Encrypt data specifications] + + +vcom Message # 1318: +When the expression of a CASE statement, selected signal assignment +statement, or selected variable assignment statement (2008 only) is of a +one-dimensional character array type, that array type must have a +locally static element subtype. The text stating this requirement was +inadvertently dropped from the 2008 LRM. + +[DOC: IEEE Std 1076-1993 VHDL LRM - 8.8 Case statement] +[DOC: IEEE Std 1076-2008 VHDL LRM - 10.9 Case statement] + + +vcom Message # 1319: +All choices other than the OTHERS choice in a CASE statement, selected +signal assignment statement, or selected variable statement must have +the same length when the expression of the statement is of an array type. +[DOC: IEEE Std 1076-2008 VHDL LRM - 10.9 Case statement] + + +vcom Message # 1320: +The expression of each element association of an array aggregate can be +of the element type or the type of the aggregate itself. When an array +aggregate is of an array type whose element subtype is composite, it is +possible for certain kinds of its element association expressions to be +interpreted as being potentially either of these two types. This will +normally happen only if the ambiguous expression is itself an aggregate +(because the type of an aggregate must be determined solely from the +context in which the aggregate appears, excluding the aggregate itself +but using the fact that the type of the aggregate shall be a composite +type) or a function call that identifies two overloaded functions. +This ambiguity is resolved in favor of the element type to support +backwards compatibility with prior versions of VHDL, in which the +element type was the only type considered. +[DOC: IEEE Std 1076-2008 VHDL LRM - 9.3.3.3 Array aggregates] + + +vcom Message # 1321: +If the type of the expression of an element association is the type of +the aggregate, then either the element association shall be positional +or [each of] the choice[s] shall be (a) discrete range[s]. +[DOC: IEEE Std 1076-2008 VHDL LRM - 9.3.3.3 Array aggregates] + + +vcom Message # 1322: +The array length and/or the value of the choice cannot be computed +because the choice is not locally static. (A choice that is not +locally static is a non-compliant extension to the language that we +provide.) It it not possible to make sure that the set of choices +contains no duplicate representations and/or that all the choices are of +the same length. +[DOC: IEEE Std 1076-2008 VHDL LRM - 10.9 Case statement] + + +vcom Message # 1323: +The compiler currently cannot evaluate the array length and/or the value +of the locally static choice. Therefore it not possible to check that +the set of choices contains no duplicate representations and/or that all +the choices are of the same array length. +This capability will be available in a future release. +Please contact http://supportnet.mentor.com. +[DOC: IEEE Std 1076-2008 VHDL LRM - 10.9 Case statement] +[DOC: IEEE Std 1076-2008 VHDL LRM - 11.8 Generate statements] + + +vcom Message # 1324: +For an element association with a choice that is a discrete range and an +expression of the type of the aggregate, each element of the value of +the expression is the value of the element of the aggregate at the +matching index value in the range. It is an error if the length of the +discrete range differs from the length of the value of the expression. +[DOC: IEEE Std 1076-2008 VHDL LRM - 9.3.3.3 Array aggregates] + + +vcom Message # 1325: +It is an error if the direction of the index range of an aggregate is +determined by the context, and an element association has a choice that +is a discrete range and an expression that is of the type of the +aggregate, and the direction of the discrete range differs from that of +the index range of the aggregate. +[DOC: IEEE Std 1076-2008 VHDL LRM - 9.3.3.3 Array aggregates] + + +vcom Message # 1326: +If an aggregate has a given element association with a choice that is a +discrete range and an expression that is of the type of the aggregate, +then it is an error if any other element association has a choice that +is a discrete range whose direction differs from that of the choice of +the given element association. +[DOC: IEEE Std 1076-2008 VHDL LRM - 9.3.3.3 Array aggregates] + + +vcom Message # 1327: +For a matching case statement, selected signal assignment statement, or +selected variable assignment statement in which the expression is of type +STD_ULOGIC, or an array type whose element type is STD_ULOGIC, it is an +error if the value of the expression is the scalar value '-' or an array +value containing the value '-'. +[DOC: IEEE Std 1076-2008 VHDL LRM - 10.9 Case statement] + + +vcom Message # 1328: +For a matching case statement, selected signal assignment statement, or +selected variable assignment statement in which the expression is of type +STD_ULOGIC, or an array type whose element type is STD_ULOGIC, it is an +error if the value of the expression is the scalar value '-' or an array +value containing the value '-'. +[DOC: IEEE Std 1076-2008 VHDL LRM - 10.9 Case statement] + + +vcom Message # 1329: +A choice given in the specified statement was a null range. +This choice will never match the expression value and will otherwise +have no effect. +This is for information only as it is not illegal. + + +vcom Message # 1330: +A choice appearing in a CASE statement, selected signal assignment +statement, or selected variable assignment statement cannot be an +aggregate with an OTHERS choice unless the statement expression is one +of the following: + + -- The name of an object whose subtype is locally static + -- An indexed name whose prefix is one of the members of this list + and whose indexing expressions are locally static expressions + -- A slice name whose prefix is one of the members of this list and + whose discrete range is a locally static discrete range + -- A function call whose return type mark denotes a locally static + subtype + -- A qualified expression or type conversion whose type mark + denotes a locally static subtype + -- An expression described in this list and enclosed in parentheses + +[DOC: IEEE Std 1076-2008 VHDL LRM - 9.3.3.3 Array aggregates] + +We are strictly compliant in matching CASE statements, matching selected +signal assignment statements, and matching selected variable assignment +statements. + + +vcom Message # 1331: +A choice appearing in a CASE statement, selected signal assignment +statement, or selected variable assignment statement cannot be an +aggregate with an OTHERS choice unless the statement expression is one +of the following: + + -- The name of an object whose subtype is locally static + -- An indexed name whose prefix is one of the members of this list + and whose indexing expressions are locally static expressions + -- A slice name whose prefix is one of the members of this list and + whose discrete range is a locally static discrete range + -- A function call whose return type mark denotes a locally static + subtype + -- A qualified expression or type conversion whose type mark + denotes a locally static subtype + -- An expression described in this list and enclosed in parentheses + +[DOC: IEEE Std 1076-2008 VHDL LRM - 9.3.3.3 Array aggregates] + +We allow this in ordinary CASE statements, ordinary selected signal +assignment statements, and ordinary selected variable assignment +statements even if the array length of the statement expression is not +known but the aggregate does not violate any other restrictions on +aggregates. However, there are some drawbacks to allowing this kind of +non-compliant behavior: + +1) The requirement that each value of the subtype of the expression be + represented once and only once in the set of choices, with no other + values allowed, cannot be enforced. +2) In general, a simulator performance slowdown (relative to an + LRM-compliant statement) can be expected. +Use the -pedanticerrors switch for strict VHDL compliance to make this +an error. + +This message will be an error with the -pedanticerrors argument. + +vcom Message # 1332: +A choice appearing in a CASE statement, selected signal assignment +statement, or selected variable assignment statement cannot be an +aggregate with an OTHERS choice unless the statement expression is one +of the following: + + -- The name of an object whose subtype is locally static + -- An indexed name whose prefix is one of the members of this list + and whose indexing expressions are locally static expressions + -- A slice name whose prefix is one of the members of this list and + whose discrete range is a locally static discrete range + -- A function call whose return type mark denotes a locally static + subtype + -- A qualified expression or type conversion whose type mark + denotes a locally static subtype + -- An expression described in this list and enclosed in parentheses + +[DOC: IEEE Std 1076-2008 VHDL LRM - 9.3.3.3 Array aggregates] + +We allow this in ordinary CASE statements, ordinary selected signal +assignment statements, and ordinary selected variable assignment +statements as long as the array length of the statement expression is +known and the aggregate does not violate any other restrictions on +aggregates. The requirement that each value of the subtype of the +expression be represented once and only once in the set of choices, with +no other values allowed, will still be enforced. +Use the -pedanticerrors switch for strict VHDL compliance to make this +an error. + +This message will be an error with the -pedanticerrors argument. + +vcom Message # 1333: +For a matching case statement, selected signal assignment statement, or +selected variable assignment statement in which the expression is of +type STD_ULOGIC, or an array type whose element type is STD_ULOGIC, it +is an error if application of the predefined matching equality operator +to the values of any two distinct choices other than the choice OTHERS +gives the result '1'. +All possible values of the expression must be represented once and only +once in the set of distinct choices. Since choice values '0' and 'L', +and '1' and 'H', each represent the same values, both values cannot be +present in any two distinct choices. +[DOC: IEEE Std 1076-2008 VHDL LRM - 10.9 Case statement] + + +vcom Message # 1334: +For a matching case statement, selected signal assignment statement, or +selected variable assignment statement in which the expression is of +type STD_ULOGIC, or an array type whose element type is STD_ULOGIC, it +is an error if application of the predefined matching equality operator +to the values of any two distinct choices other than the choice OTHERS +gives the result '1'. +All possible values of the expression must be represented once and only +once in the set of distinct choices. Since choice values '0' and 'L', +and '1' and 'H', each represent the same values, both values cannot be +present in any two distinct choices. +[DOC: IEEE Std 1076-2008 VHDL LRM - 10.9 Case statement] + + +vcom Message # 1335: +The matching choice value does not represent any value of the statement +expression. For a matching case statement, selected signal assignment +statement, or selected variable assignment statement whose expression +is of type STD_ULOGIC, only the values '0' '1' 'L' 'H' and '-' are +permitted as choices; also, the expression subtype must have a value +that can be represented by such a choice value. Similarly, when the +expression is of an array type, the array choices must contain only +these values (metavalues other than '-' are not legal), and the element +subtype of the array must have at least one value value that can be +represented by any of the elements of the array choice. +[DOC: IEEE Std 1076-2008 VHDL LRM - 10.9 Case statement] + + +vcom Message # 1336: +The matching choice range does not represent any value of the statement +expression. In particular, for a matching case statement, selected +signal assignment statement, or selected variable assignment statement +in which the expression is of type STD_ULOGIC, a choice that is a range +must contain at least one of the values '0' '1' 'L' 'H' and '-'; also, +the expression subtype must have a value that can be represented by at +least one of the values in the choice range. +[DOC: IEEE Std 1076-2008 VHDL LRM - 10.9 Case statement] + + +vcom Message # 1337: +The scalar choice value does not belong to the range of the statement +expression. This violates the "no other value is allowed" requirement +imposed on the values of the choices. +[DOC: IEEE Std 1076-1993 VHDL LRM - 8.8 Case statement] +[DOC: IEEE Std 1076-2008 VHDL LRM - 10.9 Case statement] + + +vcom Message # 1338: +The scalar range choice contains a value that does not belong to the +range of the statement expression. This violates the "no other value +is allowed" requirement imposed on the values of the choices. +[DOC: IEEE Std 1076-1993 VHDL LRM - 8.8 Case statement] +[DOC: IEEE Std 1076-2008 VHDL LRM - 10.9 Case statement] + + +vcom Message # 1339: +Each possible value of the expression must be represented once and only +once in the set of choices. +For a sequential CASE statement, if the expression is the name of an +object whose subtype is locally static (likewise, qualified expression +or type conversion with locally static type mark, or call to a function +with locally static return type), the set of possible values depends on +that locally static subtype; otherwise it depends on the base type. +For a CASE GENERATE statement, if the expression is the name of an +object whose subtype is globally static (likewise, qualified expression +or type conversion with globally static type mark, or call to a function +with globally static return type), the set of possible values depends on +that globally static subtype; otherwise it depends on the base type. +[DOC: IEEE Std 1076-1993 VHDL LRM - 8.8 Case statement] +[DOC: IEEE Std 1076-2008 VHDL LRM - 10.9 Case statement] + +This message will be an error with the -pedanticerrors argument. + +vcom Message # 1340: +For a VHDL 2008 matching case statement, selected signal assignment +statement, or selected variable assignment statement, when the statement +expression is of a type that is a one-dimensional array of STD_ULOGIC, +each value of either the subtype (when locally static) or base type of +the expression must be represented once and only once in the set of +choices. A value is represented if application of the predefined +matching equality operator to the value and the choice gives the result +'1'. An array value that contains '-' is illegal and is not considered +to be part of set of values that must be represented in the choices. If +the element subtype of the array includes one or more of the metavalues +'U', 'X', 'Z', or 'W', then the set of choices must include an OTHERS +choice, or there must be exactly one choice whose every element is the +value '-' (this may be followed optionally by an OTHERS choice, which +would represent unreachable code). +If the element subtype of the array comprises exactly '0' and '1', or +'L' and 'H', (such that no metavalues are present), then the set of +choices must represent exactly 2**N values, for a given array length N. +[DOC: IEEE Std 1076-2008 VHDL LRM - 10.9 Case statement] + + +vcom Message # 1341: +For a matching case statement, selected signal assignment statement, or +selected variable assignment statement in which the expression is of +type STD_ULOGIC, or an array type whose element type is STD_ULOGIC, it +is an error if application of the predefined matching equality operator +to the values of any two distinct choices other than the choice OTHERS +gives the result '1'. +[DOC: IEEE Std 1076-2008 VHDL LRM - 10.9 Case statement] + + +vcom Message # 1342: +For an ordinary case statement, selected signal assignment statement, or +selected variable assignment statement, it is an error if any two +choices other than the OTHERS choice have the same value. +[DOC: IEEE Std 1076-2008 VHDL LRM - 10.9 Case statement] + + +vcom Message # 1343: +For a matching case statement, selected signal assignment statement, or +selected variable assignment statement in which the expression is of type +STD_ULOGIC, or an array type whose element type is STD_ULOGIC, it is an +error if the value of the expression is the scalar value '-' or an array +value containing the value '-'. +In this case, a non-locally static value was able to be inferred to be +a constant value, so the runtime code will raise a fatal error if +executed. +[DOC: IEEE Std 1076-2008 VHDL LRM - 10.9 Case statement] + + +vcom Message # 1344: +For a matching case statement, selected signal assignment statement, or +selected variable assignment statement in which the expression is of type +STD_ULOGIC, or an array type whose element type is STD_ULOGIC, it is an +error if the value of the expression is the scalar value '-' or an array +value containing the value '-'. +In this case, a non-locally static value was able to be inferred to be +a constant value, so the runtime code will raise a fatal error if +executed. +[DOC: IEEE Std 1076-2008 VHDL LRM - 10.9 Case statement] + + +vcom Message # 1345: +For an ordinary case statement, selected signal assignment statement, or +selected variable assignment statement in which the statement expression +is of an array type and in which neither the expression nor any of the +choices has a known array length, there are some semantic checks that +will not be performed because of the non-compliant behavior being +supported. The semantic checks that will not be performed are: + 1) all values of the expression must be represented by the choices + 2) no duplicate choices are allowed + 3) all choices must be of the same array length + 4) each choice must be of the same length as the expression +[DOC: IEEE Std 1076-2008 VHDL LRM - 10.9 Case statement] + + +vcom Message # 1346: +A default expression in an interface declaration must be a globally +static expression. Use the -pedanticerrors switch for strict VHDL +compliance to make this an error. +[DOC: IEEE Std 1076-1987 VHDL LRM - 4.3.3 Interface Declarations] +[DOC: IEEE Std 1076-1993 VHDL LRM - 4.3.2 Interface declarations] +[DOC: IEEE Std 1076-2008 VHDL LRM - 6.5.2 Interface object declarations] + +This message will be an error with the -pedanticerrors argument. + +vcom Message # 1347: +It is an error if a composite type contains elements of file types or +protected types. +[DOC: IEEE Std 1076-2008 VHDL LRM - 5.3 Composite types] + + +vcom Message # 1348: +The prefix of an indexed name must be appropriate for an array type. +The prefix of a slice name must be appropriate for a one-dimensional +array object. +[DOC: IEEE Std 1076-1993 VHDL LRM - 6.4 Indexed names] +[DOC: IEEE Std 1076-1993 VHDL LRM - 6.5 Slice names] + + +vcom Message # 1349: +The type of the target of the variable or signal assignment could not be +determined. This usually occurs when the target is an aggregate and +there are several array types visible. Note that the type of an +aggregate must be determinable from the context in which it appears, and +the contents of the aggregate cannot be used. When both the target and +the right hand side of an assignment statement are aggregates, then *all* +composite types must be considered when determining the types involved, +which usually results in this error. Disambiguate the aggregate type by +using a qualified expression (type_mark'aggregate) on the right hand side. + + +vcom Message # 1350: +In an array constraint of the 2nd form, the reserved word OPEN appears +as the only lexical element enclosed in a single set of parentheses. +[DOC: IEEE Std 1076-2008 VHDL LRM - 5.3.2.1 General] + +This message will be an error with the -pedanticerrors argument. + +vcom Message # 1351: +In an array constraint of the 2nd form, the reserved word OPEN appears +as the only lexical element enclosed in a single set of parentheses. +[DOC: IEEE Std 1076-2008 VHDL LRM - 5.3.2.1 General] + + +vcom Message # 1352: +In an array constraint of the 2nd form, the type to which the reserved +word OPEN applies must be an array type or an access type whose +designated type is an array type. +[DOC: IEEE Std 1076-2008 VHDL LRM - 5.3.2.1 General] + + +vcom Message # 1353: +The type to which an element constraint applies must be either an array +type or a record type, or an access type whose designated type is an +array type or a record type. +[DOC: IEEE Std 1076-2008 VHDL LRM - 5.3.2.2 Index constraints and discrete ranges] +[DOC: IEEE Std 1076-2008 VHDL LRM - 5.3.3 Record types] +[DOC: IEEE Std 1076-2008 VHDL LRM - 6.3 Subtype declarations] + + +vcom Message # 1354: +The type to which an element constraint applies must be either an array +type or a record type, or an access type whose designated type is an +array type or a record type. +[DOC: IEEE Std 1076-2008 VHDL LRM - 5.3.2.2 Index constraints and discrete ranges] +[DOC: IEEE Std 1076-2008 VHDL LRM - 5.3.3 Record types] +[DOC: IEEE Std 1076-2008 VHDL LRM - 6.3 Subtype declarations] + + +vcom Message # 1355: +An array constraint comprises a comma-separated sequence of discrete +ranges, the reserved word OPEN, or a comma-separated sequence of record +element constraints, enclosed in set of parentheses. +A record element constraint comprises a record element simple name +followed by an element constraint. The element constraint must be +an array constraint or a record constraint, depending on the element +denoted by the record element simple name. +[DOC: IEEE Std 1076-2008 VHDL LRM - 5.3.2.1 General] +[DOC: IEEE Std 1076-2008 VHDL LRM - 5.3.3 Record types] + + +vcom Message # 1356: +A record element constraint comprises a record element simple name +followed by an element constraint. The element constraint must be +an array constraint or a record constraint, depending on the element +denoted by the record element simple name. +[DOC: IEEE Std 1076-2008 VHDL LRM - 5.3.3 Record types] + + +vcom Message # 1357: +A record constraint comprises a single set of record element constraints +enclosed in parentheses. +[DOC: IEEE Std 1076-2008 VHDL LRM - 5.3.3 Record types] + + +vcom Message # 1358: +The array constraint applies to a subtype or a subelement that is +already of a constrained array subtype. If the type mark is one of +the predefined attribute names A'ELEMENT (when A is an object) or +O'SUBTYPE, there cannot be either an array constraint or a record +constraint applied because the denoted subtypes are already fully +constrained; the only exception is when the denoted subtype is an array +type and the constraint is the reserved word OPEN. +[DOC: IEEE Std 1076-2008 VHDL LRM - 16.2.2 Predefined attributes of types and objects] +[DOC: IEEE Std 1076-2008 VHDL LRM - 5.3.2.2 Index constraints and discrete ranges] + + +vcom Message # 1359: +There are duplicate record element names in a record constraint for the +record type being constrained. Although technically not illegal, it is +presumed to be illegal and merely an oversight in the LRM. +[DOC: IEEE Std 1076-2008 VHDL LRM - 5.3.3 Record types] + + +vcom Message # 1360: +The object is declared to be of an array type that is not a constrained +array subtype. +IEEE Std 1076-2008, 5.3.2.2 Index constraints and discrete ranges + For a variable or signal [that is an array object or that is an array + subelement of a composite object] declared by an object declaration, + the subtype indication of the corresponding object declaration shall + define a fully constrained subtype (and thereby, the index range for + each index of the array object or subelement). + + +vcom Message # 1361: +The object is of a subtype that is not fully constrained. +IEEE Std 1076-2008, 5.3.2.2 Index constraints and discrete ranges + For a variable or signal [that is an array object or that is an array + subelement of a composite object] declared by an object declaration, + the subtype indication of the corresponding object declaration shall + define a fully constrained subtype (and thereby, the index range for + each index of the array object or subelement). + + +vcom Message # 1362: +In an array aggregate in which the element is of an array type (array +type is array of arrays), or in which the element is a subarray (array +type is a multidimensional array), the compiler was not able to compute +the index range of any of the expressions at a particular subelement +depth or index position. The check that each of the array expressions +is of the same array subtype or of the same length cannot be performed. +The matching element check (array length check) will be deferred until +the simulator evaluates this aggregate. + + +vcom Message # 1363: +The number of array elements present in the array aggregate does not +equal the array length at the corresponding index position. This is a +matching element test that has failed (see [7.2.2 Relational operators] +in the IEEE Std 1076-2002 LRM). + + +vcom Message # 1364: +The choice values given in the individual association elements of the +formal correspond to a different number of array elements than the type +of the formal has at that index position. +IEEE Std 1076-1993, 4.3.2.2 Association lists, line 506: + Furthermore, every scalar subelement of the explicitly declared + interface object must be associated exactly once with an actual (or + subelement thereof) in the same association list, and all such + associations must appear in a contiguous sequence within that + association list. + + +vcom Message # 1365: +When forming a null array value, the base type of the index subtype of +the array type must have at least 2 values. The pathological case here +is that the index subtype of the array type is an enumeration type with +only one enumeration literal. +[DOC: IEEE Std 1076-2008 VHDL LRM - 9.3.2 Literals] + + +vcom Message # 1366: +The implementation exhibits non-compliant behavior when a named element +association has an expression that is of the type of the element of the +aggregate and when a choice in the named element association is a range +or is OTHERS. For each such choice, the expression is evaluated only once +instead of being evaluated once for each of the elements of the array +being represented by the choice. In particular, this may have a real +effect when the expression involves an impure function call or otherwise +has side-effects. + + +vcom Message # 1367: +The LRM clause [9.3.3.3 Array aggregates] lists the places where an +aggregate (or subaggregate) with an OTHERS choice may appear. These +places generally involve a fully constrained array subtype or a slice +name. +IEEE Std 1076-2008, 9.3.3.3 Array aggregates: + The index range of an array aggregate that has an OTHERS choice shall + be determinable from the context. That is, an array aggregate with an + OTHERS choice shall appear only in one of the following contexts... + + +vcom Message # 1368: +The predefined attribute names A'ELEMENT (when A is an object) and +O'SUBTYPE cannot have either an array constraint or a record constraint +applied because the denoted subtypes are already fully constrained. +The only exception is when the denoted subtype is an array type and the +constraint is the reserved word OPEN. +[DOC: IEEE Std 1076-2008 VHDL LRM - 16.2.2 Predefined attributes of types and objects] + + +vcom Message # 1369: +The record constraint is attempting to impose an index constraint on a +record subelement that is already of a constrained array subtype. +[DOC: IEEE Std 1076-2008 VHDL LRM - 5.3.2.1 General] + + +vcom Message # 1370: +An array type or record type has a subelement of a record type. That +embedded record type itself has an element of an array type whose index +range(s) could not be determined by the compiler. For the embedded +array(s), the check that each of the array expressions is of the same +array subtype or of the same length cannot be performed. The matching +element check (array length check) will be deferred until the simulator +evaluates this aggregate. + + +vcom Message # 1371: +The predefined attribute names A'ELEMENT (when A is an object) and +O'SUBTYPE cannot have an element constraint applied because the denoted +subtype is already fully constrained. The only exception is the +reserved word OPEN applied to an array subtype in an array constraint. +[DOC: IEEE Std 1076-2008 VHDL LRM - 16.2.2 Predefined attributes of types and objects] + + +vcom Message # 1372: +Expecting a record element name here, but found it in a context that +is not part of a valid record constraint. + + +vcom Message # 1373: +The record type was compiled with VHDL 2008 and is either unconstrained +or partially constrained. It cannot be used in any language version +prior to VHDL 2008. + + +vcom Message # 1380: +The name is ambiguous according to the visibility rules. +IEEE Std 1076-1993, 10.4 Use clauses, line 234: + Potentially visible declarations that have the same designator are not + made directly visible unless each of them is either an enumeration + literal specification or the declaration of a subprogram (either by a + subprogram declaration or by an implicit declaration). +======================================================================== +NOTE: Suppressing this message is STRONGLY discouraged because of the + non-compliant nature of this feature. Suppressing this message is + recommended ONLY for those legacy designs that will not compile + without suppressing this message, and only when those designs + cannot be modified to make them VHDL compliant. Note that this + message cannot have its severity level reduced to NOTE or WARNING. +If the list of potentially visible declarations comprises only +subprograms, enumeration literals, and/or physical units, then this +message can be suppressed so that physical unit(s) are treated as +overloadable in the same manner that enumeration literals are +overloadable. The signature of an overloadable physical unit can be +considered to be + [RETURN ] +======================================================================== + + +vcom Message # 1381: +The identifier could not be determined to be either a function call or +an enumeration literal because there are visible declarations for both +that can be used in this context. + + +vcom Message # 1382: +The VHDL 2002 LRM prohibits evaluating a primary that denotes a shared +variable or a method of the protected type of a shared variable during +the elaboration of a declarative item. +Protected types were not introduced until VHDL 2002, at which point +shared variables are required to be of a protected type (QuestaSim does +not enforce this restriction). Because shared variables existed prior +to VHDL 2002, QuestaSim enforces the prohibition on evaluating shared +variables during elaboration of a declarative item if and only if the +shared variable is of a protected type. +[DOC: IEEE Std 1076-2002 VHDL LRM - 12.3 Elaboration of a declarative part] + + +vcom Message # 1383: +Because neither the port nor the actual expression is fully constrained, +it is impossible to form a legal signal declaration for the implicit +signal required to make the connection between the port and the +non-static (or INERTIAL) actual expression. +[DOC: IEEE Std 1076-2008 VHDL LRM - 6.5.6.3 Port clauses]: +If the actual part of a given association element for a formal port of a +block is the reserved word INERTIAL followed by an expression, or is an +expression that is not globally static, then the given association +element is equivalent to association of the port with an anonymous +signal implicitly declared in the declarative region that immediately +encloses the block. The signal has the same subtype as the formal port... + + +vcom Message # 1384: +The expression in each element association of an aggregate target of +either a variable assignment statement or a signal assignment statement +must be a static name. +QuestaSim relaxes this rule when the expression is an aggregate itself to +allow subaggregates (for multidimensional array types) and other +aggregates appearing inside an outer aggregate to be used, even though +technically an aggregate (subaggregate or not) is not a static name. +[DOC: IEEE Std 1076-2008 VHDL LRM - 10.5.2.1 General] +[DOC: IEEE Std 1076-2008 VHDL LRM - 10.6.2.1 General] + + +vcom Message # 1385: +The expression in each element association of an aggregate target of +either a variable assignment statement or a signal assignment statement +must be a static name. +[DOC: IEEE Std 1076-2008 VHDL LRM - 10.5.2.1 General] +[DOC: IEEE Std 1076-2008 VHDL LRM - 10.6.2.1 General] + + +vcom Message # 1386: +The direction of the index range of an array aggregate target of a +variable assignment or signal assignment statement is computed according +to the rules given in [9.3.3.3 Array aggregates] in the 2008 LRM. When +the aggregate is a named array aggregate, none of whose choices is a +range, this direction is the direction of the index subtype of the base +array type. This warning is produced when the choices of the element +associations of the aggregate are arranged in a lexical order that seems +to imply a desired direction that is the opposite of the correct +direction. +[DOC: IEEE Std 1076-2008 VHDL LRM - 9.3.3.3 Array aggregates] + + +vcom Message # 1387: +The direction of the index range of an array aggregate target of a +variable assignment or signal assignment statement is different from the +array value of the right hand side of the assignment statement. + + +vcom Message # 1388: +IEEE Std 1076-1993, 7.3.6 Allocators, line 545 + If an allocator includes a subtype indication and if the type of the + object created is an array type, then the subtype indication must + either denote a constrained subtype or include an explicit index + constraint. +IEEE Std 1076-2008, 9.3.7 Allocators + If an allocator includes a subtype indication and if the type of the + object created is an array type or a record type, then the subtype + indication shall denote fully constrained subtype. + + +vcom Message # 1389: +An array aggregate with an OTHERS choice cannot appear as the operand of +an operator that has the operand declared to be of an unconstrained +array type. +The LRM clause [9.3.3.3 Array aggregates] lists the places where an +aggregate (or subaggregate) with an OTHERS choice may appear. These +places generally involve a fully constrained array subtype or a slice +name. +IEEE Std 1076-2008, 9.3.3.3 Array aggregates: + The index range of an array aggregate that has an OTHERS choice shall + be determinable from the context. That is, an array aggregate with an + OTHERS choice shall appear only in one of the following contexts... + + +vcom Message # 1390: +The number of indices in an indexed name must match the number of index +positions in the array type of the prefix (the dimensionality of the +array type of the prefix. +Similarly, an index constraint in a subtype indication must have the +same number of discrete ranges as there are index positions in the array +type being constrained. + + +vcom Message # 1391: +The type of the object created by an allocator must be the designated +of some access type. A common mistake is to follow the reserved word +NEW with a subtype indication or a qualified expression whose base type +is the access type instead of the access type's designated type. +[DOC: IEEE Std 1076-2008 VHDL LRM - 9.3.7 Allocators + + +vcom Message # 1392: +The predefined attributes S'DELAYED, S'STABLE, and S'QUIET must not have +a parameter that is a negative value of TIME. The parameter value has +an apparent negative value because it is, or is derived from, a TIME +literal that has an abstract literal multiplier that is a negative +number. The simulator will truncate a negative TIME value to 0. This +message can be suppressed or have its severity level changed. +[DOC: IEEE Std 1076-1993 VHDL LRM - 14.1 Predefined attributes], line 243 + + +vcom Message # 1393: +The TIME expression following the reserved word REJECT must have neither +a negative value nor a value that is greater than the TIME expression +associated with the first waveform element. +This message can be suppressed or have its severity level changed. +[DOC: IEEE Std 1076-1993 VHDL LRM - 8.4 Signal assignment statement], line 194 + + +vcom Message # 1394: +A type conversion comprises a type mark and a single expression enclosed +in parentheses. The expression must not be a range and must not be the +literal NULL, an allocator, an aggregate, or a string literal +[DOC: IEEE Std 1076-1993 VHDL LRM - 7.3.5 Type conversions], line 490 + + +vcom Message # 1395: +A type conversion comprises a type mark and a single expression enclosed +in parentheses. The expression (operand) must not be a range and must +not be the literal NULL, an allocator, an aggregate, or a string literal +[DOC: IEEE Std 1076-1993 VHDL LRM - 7.3.5 Type conversions], line 490 + + +vcom Message # 1396: +IEEE Std 1076-1993, 4.3.2.1 Interface lists, line 414 + A name that denotes an interface object may not appear in any + interface declaration within the interface list containing the denoted + interface object except to declare this object. + +IEEE Std 1076-2008, 6.5.6.1 General: + A name that denotes an interface object declared in a port interface + list or a parameter interface list shall not appear in any interface + declaration within the interface list containing the denoted interface + object except to declare this object. A name that denotes an interface + declaration in a generic interface list may appear in an interface + declaration within the interface list containing the denoted interface + declaration. + + +vcom Message # 1397: +IEEE Std 1076-1993, 2.6 Package bodies, line 453 + Within a package declaration that contains the declaration of a + deferred constant, and within the body of that package (before the end + of the corresponding full declaration), the use of a name that denotes + the deferred constant is only allowed in the default expression for a + local generic, local port, or formal parameter. The result of + evaluating an expression that references a deferred constant before + the elaboration of the corresponding full declaration is not defined + by the language. + + +vcom Message # 1398: +IEEE Std 1076-1993, 2.6 Package bodies, line 453 + Within a package declaration that contains the declaration of a + deferred constant, and within the body of that package (before the end + of the corresponding full declaration), the use of a name that denotes + the deferred constant is only allowed in the default expression for a + local generic, local port, or formal parameter. The result of + evaluating an expression that references a deferred constant before + the elaboration of the corresponding full declaration is not defined + by the language. + +This message will be an error with the -pedanticerrors argument. + +vcom Message # 1399: +The file does not contain data that is compatible with what is expected +for the product, product version, or platform. + + +vcom Message # 1400: +The signal is read by at least one of the statements of the process +statement but does not appear in the sensitivity list of the process. + + +vcom Message # 1401: +The signal appears in the sensitivity list of the process but is not +being read in any of the statements in the process statement. + + +vcom Message # 1410: +See the VITAL LRM as indicated in the message. + + +vcom Message # 1411: +See the VITAL LRM as indicated in the message. + + +vcom Message # 1412: +See the VITAL LRM as indicated in the message. + + +vcom Message # 1413: +See the VITAL LRM as indicated in the message. + + +vcom Message # 1414: +See the VITAL LRM as indicated in the message. + + +vcom Message # 1415: +See the VITAL LRM as indicated in the message. + + +vcom Message # 1416: +See the VITAL LRM as indicated in the message. + + +vcom Message # 1417: +See the VITAL LRM as indicated in the message. + + +vcom Message # 1418: +See the VITAL LRM as indicated in the message. + + +vcom Message # 1419: +See the VITAL LRM as indicated in the message. + + +vcom Message # 1420: +See the specification for the DVFS prototype. + + +vcom Message # 1421: +See the specification for the DVFS prototype. + + +vcom Message # 1422: +See the specification for the DVFS prototype. + + +vcom Message # 1423: +See the specification for the DVFS prototype. + + +vcom Message # 1424: +Since external names denote declared objects, and since subelements of a +declared object are not themselves declared objects, it is not legal to +denote an element of a record object using an external name. +Rather, an external name denoting the declared object (of a record type) +can be used as the prefix of a selected name; the suffix of the selected +name shall denote the element of the record. +[DOC: IEEE Std 1076-2008 VHDL LRM - 6.4.2.1 General] +[DOC: IEEE Std 1076-2008 VHDL LRM - 8.7 External names] + + +vcom Message # 1425: +This is a warning about non-compliant behavior with respect to absolute +pathnames in VHDL external names. Absolute VHDL external names require +that the first pathname element be the name of the root design entity. +Early releases incorrectly allowed the root design name to be omitted +and would use the design root in which the external name occurs to be +used as the starting point of the external name absolute path. Now the +behavior is first to search the design roots for a matching entity name. +If that fails, then the old non-compliant behavior is used to try to +resolve the pathname. +[DOC: IEEE Std 1076-2008 VHDL LRM - 8.7 External names] + + +vcom Message # 1426: +The syntax for an attribute declaration requires a type mark, not a +subtype indication, after the ':' delimiter. A type mark is the name of +a type or subtype and does not contain a constraint. + +This message will be an error with the -pedanticerrors argument. + +vcom Message # 1427: +An element association with more than one choice, or with the choice +OTHERS, is only allowed if the elements specified are all of the same +type. +[DOC: IEEE Std 1076-1993 VHDL LRM - 7.3.2.1 Record aggregates] + + +vcom Message # 1428: +IEEE Std 1076-1993, 3.2.2 Record types, line 473: + The use of a name that denotes a record element is not allowed within + the record type definition that declares the element. + + +vcom Message # 1429: +The value of a signal is not defined until after the design hierarchy is +elaborated. Use of the signal name in a declarative item is prohibited +because the value is undefined until the entire design has been +elaborated. +[DOC: IEEE Std 1076-1993 VHDL LRM - 12.3 Elaboration of a declarative part] + + +vcom Message # 1430: +A VHDL external name can denote only an object declared in the +declarative region of an Entity, an Architecture, a Block statement, a +Generate statement, or a Package declaration. A generic or port of an +Entity can also be denoted. +However, in particular, an external name cannot denote an object +declared in a PROCESS statement or a Subprogram. +[DOC: IEEE Std 1076-2008 VHDL LRM - 8.7 External names] + + +vcom Message # 1431: +A limitation of the implementation of protected types requires that a +FILE object declaration inside a protected type body be of a file type +that was compiled with language version 1993 or later. + + +vcom Message # 1432: +If a generic list contains an interface element that is an interface +type declaration, then any corresponding GENERIC MAP aspect must contain +a corresponding subtype indication actual. +[DOC: IEEE Std 1076-2008 6.5.3 Interface type declarations] +[DOC: IEEE Std 1076-2008 6.5.7.2 Generic map aspects] + + +vcom Message # 1433: +IEEE Std 1076-2008 6.5.5 Interface package declarations. +The interface package element must contain the name of an uninstantiated +package. + + +vcom Message # 1434: +Reserved word INERTIAL in an association element of an association list +can appear only in a PORT MAP aspect, and only when the PORT to which it +applies is of mode IN. It is not valid in a GENERIC MAP aspect or in a +subprogram association list. +[DOC: IEEE Std 1076-1993 VHDL LRM - 1.1.1.2 Ports] + Moreover, the ports of a block may be associated with an expression in + order to provide these ports with constant driving values; such ports + must be of mode in. +[DOC: IEEE Std 1076-2008 VHDL LRM - 6.5.6.3 Port clauses] + Moreover, the ports of a block may be associated with an expression in + order to provide these ports with constant driving values or with + values derived from signals and other ports; such ports shall be of + mode in. +[DOC: IEEE Std 1076-2008 VHDL LRM - 6.5.7.1 General] + It is an error if the reserved word INERTIAL appears in an association + element other than in a port map aspect. + + +vcom Message # 1435: +Reserved word INERTIAL in an association element of an association list +can appear only for a port that is of mode IN. +[DOC: IEEE Std 1076-2008 VHDL LRM - 6.5.6.3 Port clause] + + +vcom Message # 1436: +VHDL 1993 through VHDL 2002 allowed an expression to be associated with +a formal port in a port map as long as the expression was globally +static and the port was of mode IN. VHDL 2008 now allows non-static +expressions as well. Use the -2008 switch to vcom to enable this +feature. +[DOC: IEEE Std 1076-2002 VHDL LRM - 1.1.1.2 Ports] +[DOC: IEEE Std 1076-2008 VHDL LRM - 6.5.6.3 Port clause] + + +vcom Message # 1438: +The reserved word INERTIAL preceding an actual expression in a port map +causes the creation of an implicit signal to represent the value; this +in turn causes a delta to be inserted between the expression and the +formal. In this case, the expression is static so normally the implicit +signal and the delta delay would not be present, but the inclusion of +INERTIAL causes the expression to be treated as though it were not +static. This is not illegal, it is just a bit unorthodox. +[DOC: IEEE Std 1076-2008 VHDL LRM - 6.5.6.3 Port clause] + + +vcom Message # 1439: +It is an error if a process statement with the reserved word ALL as its +process sensitivity list is the parent of a subprogram declared in a +design unit other than that containing the process statement, and the +subprogram reads an explicitly declared signal that is not a formal signal +parameter or member of a formal signal parameter of the subprogram or of +any of its parents. Similarly, it is an error if such a subprogram reads +an implicit signal whose explicit ancestor is not a formal signal parameter +or member of a formal parameter of the subprogram or of any of its parents. +[DOC: IEEE Std 1076-2008 VHDL LRM - 11.3 Process Statement] + +This is warning in the incr flow because the sensitivity is correctly formed without +sensitivity to the non-parameter signal read, and incremental compilation rules +allow the package body to be revised later, possibly removing this read. + + +vcom Message # 1440: +The specified language feature is not supported yet. + + +vcom Message # 1441: +This version of the language does not support the specified language +feature. + + +vcom Message # 1442: +IEEE Std 1076-2008 6.5.6.2 Generic clauses. +Interface type declarations, interface subprogram declarations, and +interface package declarations can appear only in GENERIC interface +lists. + + +vcom Message # 1443: +If a generic list contains an interface element that is an interface +package declaration, then any corresponding GENERIC MAP aspect must +contain a corresponding package instance actual that specifies an +instance of the package named in the formal generic package declaration. +[DOC: IEEE Std 1076-2008 6.5.5 Interface package declarations] +[DOC: IEEE Std 1076-2008 6.5.7.2 Generic map aspects] + + +vcom Message # 1444: +It is illegal syntax if another expression appears in a sensitivity list +along with reserved word ALL. +[DOC: IEEE Std 1076-2008 VHDL LRM - 11.3 Process statement] + + +vcom Message # 1445: +The sensitivity list contains a duplicate signal name. Perhaps this is +a typographical error. + + +vcom Message # 1446: +This is is illegal syntax and may involve attempting to use a reserved +word as an identifier. + + +vcom Message # 1447: +A default binding selected an entity that doesn't have any architectures. +Therefore the component instance will be unbound (open). To avoid this, +either an architecture needs to be compiled for this entity, or there +needs to be an explicit binding indication specified in a configuration +specification or a component configuration. + + +vcom Message # 1448: +The syntax for a bit string literal is: + [ integer ] base_specifier"[ bit_value ]" +[DOC: IEEE Std 1076-2008 VHDL LRM - 15.8 Bit string literals] + + +vcom Message # 1449: +When the specified length of a bit string literal is less than the +number of characters in the expanded bit value, characters are deleted +from the left of the expanded bit value so that the number of remaining +characters in the expanded bit value equals the specified length. +For an unsigned bit string literal all the deleted characters must be 0. +For a signed bit string literal all the deleted characters must be the same +as the leftmost remaining character in the expanded bit value. +[DOC: IEEE Std 1076-2008 VHDL LRM - 15.8 Bit string literals] + + +vcom Message # 1450: +The actual designator must be a static signal name. +In particular, the actual signal associated with a class signal +subprogram parameter, or the actual signal associated with a port in a +port map, must be a static signal name. +In VHDL 2008, a non-static signal name is considered to be a non-static +expression and will adhere to the semantics for that. +[DOC: IEEE Std 1076-2008 VHDL LRM - 4.2.2.3 Signal parameters, + - 6.5.6.3 Port clauses, + - 8.1 General] + + +vcom Message # 1451: +The actual designator is not a static signal name, it is an expression. +In a VHDL 1987 port map, the actual designator in an association element +must be either a static signal name or a conversion function call whose +only argument is a static signal name. +In a subprogram association list in any VHDL language version, the +actual associated with a class SIGNAL subprogram parameter must be a +static signal name. +Later versions of VHDL allow flexibility in the actual in a port map. +Try using the -93, -2002, or -2008 switch to vcom. +[DOC: IEEE Std 1076-1987 VHDL LRM - 2.1.1.2 Signal parameters, + 4.3.3.2 Association Lists] +[DOC: IEEE Std 1076-1993 VHDL LRM - 2.1.1.2 Signal parameters] + + +vcom Message # 1452: +An element of a record type can have at most one resolution indication +associated with it in a subtype indication. +[DOC: IEEE Std 1076-2008 VHDL LRM - 6.3 Subtype declarations] + + +vcom Message # 1453: +A record element resolution must refer to an element of the record type. +[DOC: IEEE Std 1076-2008 VHDL LRM - 6.3 Subtype declarations] + + +vcom Message # 1454: +VHDL 1993 and later allows an expression to be used as the actual for a +formal port as long as the port is of mode IN. However, if the port is +a component port and it is of mode INOUT, we will allow an expression as +the actual as long as the entity port that the component port binds to +is of mode IN and the expression is globally static. + + +vcom Message # 1455: +It is an error if the context clause preceding a library unit that is a +context declaration is not empty. +No LIBRARY clauses, USE clauses, or CONTEXT references may appear before +the start of a CONTEXT declaration. +[DOC: IEEE Std 1076-2008 VHDL LRM - 13.1 Design units] + + +vcom Message # 1456: +Library clauses, use clauses and context references within a context +declaration must not refer to the library logical name WORK. +[DOC: IEEE Std 1076-2008 VHDL LRM - 13.3 Context Declarations] + + +vcom Message # 1457: +The actual associated with an interface type (generic type) must be a +subtype indication. + + +vcom Message # 1458: +Signals, Constants and Generics may not be of an access type or of a +composite type that contains an access type. +[DOC: IEEE Std 1076-2008 VHDL LRM - 6.4.2.2 Constant declarations, + 6.4.2.3 Signal declarations] + + +vcom Message # 1459: +The previous errors and warnings occurred when loading or instantiating +a related externally declared declaration, as happens with: + -- a package instantiation of an uninstantiated package declaration + -- a context reference to a context declaration + + +vcom Message # 1460: +Constants may not be of a protected type. +[DOC: IEEE Std 1076-2008 VHDL LRM - 6.4.2.2 Constant declarations] + + +vcom Message # 1461: +Constants may not be of a file type. +[DOC: IEEE Std 1076-2008 VHDL LRM - 6.4.2.2 Constant declarations] + + +vcom Message # 1462: +Constants may not be of an access type or of a composite type that +contains an access type. +[DOC: IEEE Std 1076-2008 VHDL LRM - 6.4.2.2 Constant declarations] + + +vcom Message # 1463: +Constants and variables may not be of an incomplete type or of a +composite type that contains an incomplete type. +[DOC: IEEE Std 1076-2008 VHDL LRM - 5.4.2 Incomplete type declarations] + + +vcom Message # 1464: +Signals may not be of a protected type. +[DOC: IEEE Std 1076-2008 VHDL LRM - 6.4.2.3 Signal declarations] + + +vcom Message # 1465: +Signals may not be of a file type. +[DOC: IEEE Std 1076-2008 VHDL LRM - 6.4.2.3 Signals declarations] + + +vcom Message # 1466: +Signals may not be of an access type or of a composite type that +contains an access type. +[DOC: IEEE Std 1076-2008 VHDL LRM - 6.4.2.3 Signal declarations] + + +vcom Message # 1467: +Signals may not be of an incomplete type or of a composite type that +contains an incomplete type. +[DOC: IEEE Std 1076-2008 VHDL LRM - 5.4.2 Incomplete type declarations] + + +vcom Message # 1468: +In VHDL 1993 and later, objects of a file type must be of class FILE. + + +vcom Message # 1469: +In VHDL 1987, objects of a file type must be of class VARIABLE. + + +vcom Message # 1470: +If an interface subprogram declaration contains an interface subprogram +default in the form of a subprogram name, the subprogram name shall +denote a subprogram[.] +[DOC: IEEE Std 1076-2008 VHDL LRM - 6.5.4 Interface subprogram declarations] + + +vcom Message # 1471: +The actual (subtype indication) associated with an interface type in an +association list cannot be a protected type or a file type. While there +is no normative text to establish these restrictions, Note 6 in +[6.4.2.4 Variable declarations] and Note 2 in +[6.4.2.5 File declarations] assert these restrictions. +[DOC: IEEE Std 1076-2008 VHDL LRM - 6.4.2.4 Variable declarations] +[DOC: IEEE Std 1076-2008 VHDL LRM - 6.4.2.5 File declarations] + + +vcom Message # 1472: +A shared variable declaration cannot have a subtype indication that is +an interface type. Shared variables must be of a protected type, and it +is illegal to associate a protected type with an interface type in an +association list. This means there is no way to establish a protected +type as the actual type of the shared variable. See message #1471 re +protected types. +We allow this with the caveat as explained in message #1236. Use the +-pedanticerrors switch for strict VHDL compliance to make this an error. +[DOC: IEEE Std 1076-2008 VHDL LRM - 6.4.2.4 Variable declarations] + +This message will be an error with the -pedanticerrors argument. + +vcom Message # 1473: +If a generic list contains an interface element that is an interface +subprogram declaration that does not include an interface subprogram +default, then the corresponding GENERIC MAP aspect must contain a +corresponding actual name that denotes a subprogram whose profile +conforms to that of the subprogram specified by the interface subprogram. +[DOC: IEEE Std 1076-2008 6.5.4 Interface subprogram declarations] +[DOC: IEEE Std 1076-2008 6.5.7.2 Generic map aspects] + + +vcom Message # 1474: +The selected name in a context reference must comprise a prefix that +denotes a library and a suffix that denotes a context declaration that +exists as a design unit in that library. + It is an error if a selected name in a context reference does not + denote a context declaration. +[DOC: IEEE Std 1076-2008 VHDL LRM - 13.4 Context clauses] + + +vcom Message # 1475: +The selected name in a context reference must comprise a prefix that +denotes a library and a suffix that denotes a context declaration that +exists as a design unit in that library. + It is an error if a selected name in a context reference does not + denote a context declaration. +[DOC: IEEE Std 1076-2008 VHDL LRM - 13.4 Context clauses] + + +vcom Message # 1476: +An actual associated with a formal generic subprogram shall be a name +that denotes a subprogram whose profile conforms to that of the formal, +or the reserved word OPEN. +[DOC: IEEE Std 1076-2008 VHDL LRM - 6.5.7.2 Generic map aspects] + + +vcom Message # 1477: +The actual associated with a formal generic subprogram must denote a +subprogram or subprogram instance whose signature conforms to the +signature of the interface subprogram. +[DOC: IEEE Std 1076-2008 VHDL LRM - 6.5.6.2 Generic clauses] + + +vcom Message # 1478: +The interface subprogram was unassociated or associated with OPEN, and +no visible subprogram conformed to the interface subprogram default +specification. + + +vcom Message # 1479: +It is an error if no actual is specified [or if it is associated with +OPEN] for a given formal generic subprogram and no interface subprogram +default is present in the corresponding interface element. +[DOC: IEEE Std 1076-2008 VHDL LRM - 6.5.6.2 Generic clauses] + + +vcom Message # 1480: +The subtype denoted by a generic type is specified by the corresponding +actual in a generic association list. It is an error if no such actual +is specified for a given generic type (either because the formal generic +is unassociated or because the actual is OPEN). +[DOC: IEEE Std 1076-2008 VHDL LRM - 6.5.6.2 Generic clauses] + + +vcom Message # 1481: +The subtype denoted by a generic type is specified by the corresponding +actual in a generic association list. It is an error if no such actual +is specified for a given generic type (either because the formal generic +is unassociated or because the actual is OPEN). +[DOC: IEEE Std 1076-2008 VHDL LRM - 6.5.6.2 Generic clauses] + + +vcom Message # 1482: +The parameter specification of a FOR LOOP or a FOR GENERATE statement +includes the reserved word IN followed by a discrete range. A discrete +range is a subtype indication or a range, the type of which must be a +discrete type (an integer type or an enumeration type). If this error +is suppressed or otherwise has its severity level downgraded, then the +subtype, not the value, of the expression will be used as the range over +which the loop iterations will occur. +Note that if the expression here is potentially illegal (for example, if +it contains an indexed name with an index value that does not satisfy +the constraint of the corresponding index range of the prefix's array +subtype), then it will not be tested for validity other than to confirm +that the subtype of the expression is of discrete type. +[DOC: IEEE Std 1070-2008 VHDL LRM - 10.10 Loop statement + 11.8 Generate statements + +This error message can be suppressed or downgraded to a note or warning. + +vcom Message # 1483: +VHDL 1993 through VHDL 2002 allowed an expression to be associated with +a formal port in a port map as long as the expression was globally +static and the port was of mode IN. VHDL 2008 now allows non-static +expressions as well. Use the -2008 switch to vcom to enable this +feature. +[DOC: IEEE Std 1076-2002 VHDL LRM - 1.1.1.2 Ports] +[DOC: IEEE Std 1076-2008 VHDL LRM - 6.5.6.3 Port clause] + + +vcom Message # 1484: +The identifier to the left of the '=>' delimiter must denote the name of +a generic, port, or subprogram parameter of the component, entity, +subprogram, block, or package being referenced. + + +vcom Message # 1485: +It is an error if the actual subprogram [associated with an interface +subprogram], whether explicitly associated or associated by default, is +IMPURE and the formal generic subprogram is PURE. +[DOC: IEEE Std 1076-2008 VHDL LRM - 6.5.6.2 Generic clauses] + +This message will be an error with the -pedanticerrors argument. + +vcom Message # 1486: +The name provided for an actual that is to be associated with an interface +subprogram must denote a unique subprogram. +[DOC: IEEE Std 1076-2008 VHDL LRM - 6.5.6.2 Generic clauses] + + +vcom Message # 1487: +For a context to have any effect it must appear in a context reference. +A context reference is the reserved word CONTEXT followed by a selected +that denotes a context declaration. +A USE clause makes certain declarations directly visible within a design +unit and does not in particular cause a context declaration to be +expanded in the same manner that a context reference does. +[DOC: IEEE Std 1076-2008 VHDL LRM - 12.4 Use clauses, 13.4 Context clauses] + + +vcom Message # 1488: +In a FOR LOOP or FOR GENERATE statement, an attribute name is allowed as +the discrete range provided the attribute is attribute of kind RANGE or +SUBTYPE. Valid attributes are RANGE, REVERSE_RANGE, SUBTYPE, and ELEMENT. +[DOC: IEEE Std 1070-2008 VHDL LRM - 10.10 Loop statement + 11.8 Generate statements + 16.1 Predefined attributes + + +vcom Message # 1489: +There are some places where an expression must be of a discrete type. +A discrete type is either an integer type or an enumeration type. +The places include: + 1 - Index constraint in a constrained array definition + 2 - Discrete range of a FOR LOOP/FOR GENERATE statement + 3 - Expression of a CASE statement + 4 - Expression of a selected signal assignment statement + 5 - Expression of a selected variable assignment statement +[DOC: IEEE Std 1070-2008 VHDL LRM - 5.3.2.1 General + 10.10 Loop statement + 11.8 Generate statements + 10.9 Case statement + 10.5.4 Selected signal assignments + 10.6.4 Selected variable assignments + + +vcom Message # 1490: +Due to compatiablity issues, the 10.1x version of VHDL does not allow signal parameters +in a VHDL-2002 scope to be passed as an actual to a VHDL-2008 out mode signal parameter. + + +vcom Message # 1491: +All source files for the compiler are empty or contain only comments and +white space characters. +At least one design unit is required. +[DOC: IEEE Std 1076-2008 VHDL LRM - 13.1 Design units + +This error message can be suppressed or downgraded to a note or warning. + +vcom Message # 1492: +In generic map aspects, every interface subprogram must be associated with +either an instance of an uninstantiated subprogram, or a simple subprogram. + + +vcom Message # 1493: +An alternative label shall not appear at the end of the generate +statement body in a FOR GENERATE statement. +[DOC: IEEE Std 1076-2008 VHDL LRM - 11.8 Generate statements + + +vcom Message # 1494: +If a label appears at the end of a generate statement body [after END] +in an IF GENERATE statement, then the immediately enclosing IF, ELSIF, +or ELSE part of the IF GENERATE statement shall include an alternative +label, and the label at the end of the generate statement body shall +repeat the alternative label. Similarly, if a label appears at the end +of a generate statement body in a CASE GENERATE, then the immediately +enclosing case generate alternative of the CASE GENERATE statement shall +include an alternative label [after WHEN], and the label at the end of +the generate statement body shall repeat the alternative label. +[DOC: IEEE Std 1076-2008 VHDL LRM - 11.8 Generate statements + + +vcom Message # 1495: +If a label appears at the end of a generate statement body [after END] +in an IF GENERATE statement, then the immediately enclosing IF, ELSIF, +or ELSE part of the IF GENERATE statement shall include an alternative +label, and the label at the end of the generate statement body shall +repeat the alternative label. Similarly, if a label appears at the end +of a generate statement body in a CASE GENERATE, then the immediately +enclosing case generate alternative of the CASE GENERATE statement shall +include an alternative label [after WHEN], and the label at the end of +the generate statement body shall repeat the alternative label. +[DOC: IEEE Std 1076-2008 VHDL LRM - 11.8 Generate statements + + +vcom Message # 1496: +The ELSE GENERATE part (if present) of an IF GENERATE statement must be +the last part present; the syntax does not allow additional IF, ELSIF, +or ELSE parts after the ELSE GENERATE part. +[DOC: IEEE Std 1076-2008 VHDL LRM - 11.8 Generate statements + + +vcom Message # 1497: +The ELSE GENERATE part (if present) of an IF GENERATE statement must be +the last part present; the syntax does not allow additional IF, ELSIF, +or ELSE parts after the ELSE GENERATE part. +[DOC: IEEE Std 1076-2008 VHDL LRM - 11.8 Generate statements + + +vcom Message # 1498: +The alternative labels, if any, within an IF GENERATE statement or a +CASE GENERATE statement shall all be distinct. +[DOC: IEEE Std 1076-2008 VHDL LRM - 11.8 Generate statements + + +vcom Message # 1499: +Aggregates containing a single element association shall always be +specified using named association in order to distinguish them from +parenthesized expressions. +[DOC: IEEE Std 1076-2008 VHDL LRM - 9.3.3.1 General aggregates] + + +vcom Message # 1500: +Internal error. The data allocation for an architecture body being +configured by a block configuration does not match that of the original +architecture body. The declaration was present in the original +architecture body but could not be found by the block configuration that +applies to this architecture body. + + +vcom Message # 1501: +Internal error. The data allocation for an architecture body being +configured by a block configuration does not match that of the original +architecture body. The declaration was present in the original +architecture body but could not be found by the block configuration that +applies to this architecture body. + + +vcom Message # 1502: +Internal error. The data allocation for an architecture body being +configured by a block configuration does not match that of the original +architecture body. The problem is with the named object. + + +vcom Message # 1503: +Internal error. The data allocation for an architecture body being +configured by a block configuration does not match that of the original +architecture body. The problem is with the subtype of the named object. + + +vcom Message # 1504: +The package denoted in the external name package pathname is an +uninstantiated package. An instance of this package must be created +first. The package instance name can then be used in an external name. +[DOC: IEEE Std 1076-2008 VHDL LRM - 8.7 External names] + + +vcom Message # 1505: +Attributes SIMPLE_NAME, INSTANCE_NAME, and PATH_NAME require their +prefix to be a named entity. This does not include subelements such as +record elements, array slices, or array elements. QuestaSim allows this +non-standard prefix, but the string value of the attribute name will not +include the subelement information. +[DOC: IEEE Std 1076-2008 VHDL LRM - 16.2.5 Predefined attributes of named entities] +[DOC: IEEE Std 1076-2008 VHDL LRM - 7.2 Attribute specification] + + +vcom Message # 1506: +No parameter and result type profile of any candidate uninstantiated +subprogram matched the signature specified in the instantiation +declaration. Check that the signature exactly matches a parameter and +result type profile of a visible uninstantiated subprogram, and that any +interface type names are different from other declared identifiers in +the same scope. + + +vcom Message # 1507: +The return type of the conversion function, in conjunction with the +array index range(s), if any, defined for the subtype indication of the +formal, must result in every array subelement of the value having an +index range. +[DOC: IEEE Std 1076-2008 VHDL LRM - 5.3.2.2 Index constraints and discrete ranges] + +This message will be an error with the -pedanticerrors argument. + +vcom Message # 1508: +The type mark, in conjunction with the array index range(s), if any, +defined for the subtype indication of the formal, must result in every +array subelement of the value having an index range. +[DOC: IEEE Std 1076-2008 VHDL LRM - 5.3.2.2 Index constraints and discrete ranges] + +This message will be an error with the -pedanticerrors argument. + +vcom Message # 1509: +IEEE Std 1076-1993, 2.6 Package bodies, line 449 + If a given package declaration contains a deferred constant + declaration (see 4.3.1.1), then a constant declaration with the same + identifier must appear as a declarative item in the corresponding + package body. This object declaration is called the full declaration + of the deferred constant. + + +vcom Message # 1510: +An access value belongs to a corresponding subtype of an access type +either if the access value is the NULL value or if the value of the +designated object satisfies the constraint. +[DOC: IEEE Std 1076-2008 VHDL LRM - 5.4 Access types] + +A composite value that includes array subelements must be such that all +array subelements have index ranges that are identical in bounds and +direction to the index ranges implied by the union of the constraint +(if any) present in an access subtype definition and the constraint (if +any) present in the subtype indication used in the access type +definition. +Example: + type rec is record + f1 : bit_vector; + f2 : bit_vector(1 to 3); + f3 : string; + end record; + type acc is access rec(f3(1 to 4)); + subtype sub is acc(f1(3 to 5)); + -- Objects designated by type "acc" must have the following index + -- ranges: + -- f1 -- any index range that satisfies NATURAL, direction irrelevant + -- f2 -- (1 to 3) + -- f3 -- (1 to 4) + -- Objects designated by subtype "sub" must have have the following + -- index ranges: + -- f1 -- (3 to 5) + -- f2 -- (1 to 3) + -- f3 -- (1 to 4) + + +vcom Message # 1511: +The native code of the specified VHDL configuration will not be +refreshed. +The native code of a VHDL configuration can be refreshed only after all +the architectures on which it depends have also had their native code +refreshed. Architectures that reside in the same library as the +configuration are handled automatically by causing them to be refreshed +first (including their native code), but architectures that reside in +different libraries must be refreshed (including their native code) by +the user before the configuration can be refreshed. The message +contains a list of all the dependent architectures that do not reside in +the same library as the configuration and either + (1) have no native code, or + (2) for which the existing native code was created with a different + major release version of the compiler. + + +vcom Message # 1512: +The native code of the specified VHDL configuration could not be created +because it contains a block configuration that configures an +architecture for which no native code was found. This can happen if the +configuration is compiled using -novopt, but an architecture on which it +depends was compiled without -novopt. If a configuration is to be +compiled with -novopt, then make sure that all the architectures on +which it depends have been compiled or otherwise refreshed with -novopt +as well. This message might be followed by another message that gives +more information about the problem. + + +vcom Message # 1513: +The protected type has a CONSTANT data member of an unconstrained or +partially constrained subtype. The expression in the declaration is +such that the fully constrained subtype cannot be determined by the +compiler. QuestaSim does not support this yet. +Please contact support@model.com. + + +vcom Message # 1514: +This is an informational warning. When an aggregate does not contain a +named element association that has a choice that is a range and that has +an expression that is of the type of the aggregate, when that aggregate +appears at a place where an OTHERS choice in the aggregate would not be +allowed, the direction of the aggregate is obtained from the direction +of the index subtype of the base array type (at the applicable index +position), not from the direction of the range choice(s) of the element +association(s). +The range choice(s) have no effect on the direction of the aggregate. +[DOC: IEEE Std 1076-2008 VHDL LRM - 9.3.3.3 Array aggregates] + + +vcom Message # 1515: +The predefined attributes A'LEFT, A'RIGHT, A'HIGH, A'LOW, A'RANGE, +A'REVERSE_RANGE, A'LENGTH, and A'ASCENDING (and A'ELEMENT for VHDL 2008) +each require that "A" be appropriate for an array object or an alias +thereof, or that it denote an array type or subtype. A function call +does not satisfy this requirement. Legacy requires that we allow this; +the function will be called, and its return value will be used to +determine the effect of this attribute name. +Use the -pedanticerrors switch for strict VHDL compliance to make this +an error. +[DOC: IEEE Std 1076-1993 VHDL LRM - 14.1 Predefined attributes] +[DOC: IEEE Std 1076-2008 VHDL LRM - 16.2.3 Predefined attributes of arrays] + +This message will be an error with the -pedanticerrors argument. + +vcom Message # 1516: +The package STD.ENV does not exist in this version of the language, it +was added in VHDL 2008. Please use the appropriate language version +(i.e. "-2008") when compiling. We allow this for ease of use when a +design contains design units compiled with a mix of language versions. +Use the -pedanticerrors switch for strict VHDL compliance to make this +an error. + +This message will be an error with the -pedanticerrors argument. + +vcom Message # 1517: +IEEE Std 1076-2008, 6.3 Subtype declarations: +A subtype indication denoting a subtype of a file type, a protected +type, or a formal generic incomplete type of an uninstantiated package +or subprogram declaration shall not contain a constraint. +QuestaSim extends this restriction to any interface type in the belief +that this is the intent of the LRM. + + +vcom Message # 1518: +The configuration declaration has the same name as the entity that it is +configuring. Since libraries cannot have two design units with the same +name, the configuration design unit would overwite the entity design +unit, resulting in a design that cannot be loaded (because the entity +would not exist, having been overwritten by the configuration). + + +vcom Message # 1519: +Internal error. The named object appears to be a CONSTANT that has no +expression in its declaration. +Please contact http://supportnet.mentor.com + + +vcom Message # 1520: +The binding indication that implies a Verilog design unit contains an +architecture name. Since Verilog design units do not have secondary +design units, this architecture name will ignored. The entity aspect of +the binding indication of course must contain the reserved word ENTITY +(not CONFIGURATION) when it implies a Verilog Module. + + +vcom Message # 1521: +A component configuration including a binding indication that implies a +Verilog design unit cannot have an inner block configuration because +configuring across the language boundary is not supported. +The exception that is allowed occurs when there are no configuration +items in the block configuration. This requires that the relevant +binding indication contain an architecture name (which is generally +ignored, see message #1520) and that the inner block configuration block +specification denote the same architecture name. + + +vcom Message # 1522: +The design pathname contains the name of a label of a GENERATE statement +whose active branch (if any) cannot be determined until the design is +loaded, and the name of this GENERATE statement label is followed by a +design pathname element that presumably would be found in this active +branch (as either an object or a scope). Each possible generate branch +will be searched for an object or scope with this design pathname +element name. + + +vcom Message # 1523: +A design pathname contains the name of a label of a GENERATE statement +whose active branch (if any) cannot be determined until the design is +loaded, and the name of this GENERATE statement label is followed by a +name that presumably would be found in this active branch (as either an +object or a scope). This name does not exist in any of the possible +branches of the GENERATE statement and thus the design pathname cannot +represent anything in the design. Objects declared immediately in each +of the possible generate branches will be made visible to ensure that +the actual active branch (if there is one) has its objects visible. + + +vcom Message # 1524: +A design pathname contains the name of a label of a GENERATE statement +whose active branch (if any) cannot be determined until the design is +loaded, and the name of this GENERATE statement label is followed by a +name that presumably would be found in this active branch (as either an +object or a scope). Although the name immediately following the +generate statement label name has been found as a scope in at least one +of the possible generate branches, the name(s) following the presumed +scope name is/are being ignored because there is no feasible way to +track all possible objects and/or scopes that they might represent. +Therefore, each possible generate branch that has a scope with the +presumed scope name will have objects in that scope and lower made +visible. + + +vcom Message # 1525: +The predefined attribute O'SUBTYPE requires a prefix that is appropriate +for an object, or an alias thereof. Because A'ELEMENT allows A to be a +function call, QuestaSim will allow a function call prefix O here, in a +manner similar to A'ELEMENT. The function will be called, and its +return value will be used to determine the effect of this attribute +name. Note that the function will be called even if it is not necessary +to determine the resulting subtype. +Use the -pedanticerrors switch for strict VHDL compliance to make this +an error. +[DOC: IEEE Std 1076-2008 VHDL LRM - 16.2.2 Predefined attributes of types and objects] + +This message will be an error with the -pedanticerrors argument. + +vcom Message # 1526: +A range is not value; its use is limited to a fairly small set of +places in the language. There are 2 forms of ranges, attribute names +A'RANGE and A'REVERSE_RANGE, and ' '. +Neither one of these can be used in a place where a value is expected. +The predefined attribute A'LENGTH can be used to produce a value that is +the number of elements in the array A. +[DOC: IEEE Std 1076-1993 VHDL LRM - 3.1 Scalar types] +[DOC: IEEE Std 1076-1993 VHDL LRM - 14.1 Predefined attributes] + + +vcom Message # 1527: +The predefined attribute names O'SUBTYPE and A'ELEMENT can be used in +places only where a type or subtype name is legal. +[DOC: IEEE Std 1076-2008 VHDL LRM - 16.2.2 Predefined attributes of types and objects] +[DOC: IEEE Std 1076-2008 VHDL LRM - 16.2.3 Predefined attributes of arrays] + + +vcom Message # 1528: +The indicated protect directive can have the keyword specified only +once. +[DOC: IEEE Std 1076-2008 VHDL LRM - 24.1.4 Encryption envelopes] + + +vcom Message # 1529: +The array length and/or the value of the choice could not be computed. +It it not possible for the compiler to make sure that the set of choices +contains no duplicate representations and/or that all the choices are of +the same length. This check will be performed by the simulator when the +design is elaborated. +[DOC: IEEE Std 1076-2008 VHDL LRM - 11.8 Generate statements] + + +vcom Message # 1530: +The syntax for a CASE GENERATE statement does not allow the delimiter +'?' (question mark) to appear before the case expression. +[DOC: IEEE Std 1076-2008 VHDL LRM - 11.8 Generate statements] + + +vcom Message # 1531: +The condition in an IF GENERATE statement or any of its ELSIF parts +must be a (globally) static expression. It cannot depend on a signal +value or other non-static value. This is an Error if the statement +contains any ELSIF or ELSE parts. + + +vcom Message # 1532: +The expression in a FOR GENERATE statement must be globally static. +It cannot depend on a signal value or other non-static value. + + +vcom Message # 1533: +The expression did not satisfy the requirements for a CASE GENERATE +expression: +IEEE Std 1076-2008, 11.8 Generate statements: + For a CASE GENERATE statement, the expression shall be globally + static, and shall be of a discrete type, or of a one-dimensional array + type whose element base type is a character type. This type shall be + determined by applying the rules of 12.5 to the expression considered + as a complete context, using the fact that the expression shall be of + a discrete type or a one-dimensional character array type. + + +vcom Message # 1534: +A choice, whether it is a simple expression or a discrete range, that +appears in a CASE GENERATE statement, must be globally static. +It cannot depend on a signal value or other non-static value. + + +vcom Message # 1535: +A CASE GENERATE statement that has a case generate alternative in which +there appears a choice that is an array aggregate that has an OTHERS +choice is legal only when the CASE GENERATE expression is one of the +following [this is by inference from item (j) in the LRM reference cited +below]: + -- The name of an object whose subtype is globally static, in which + case the index range of the aggregate is the index range of the + subtype of the object + -- An indexed name whose prefix is one of the members of this list and + whose indexing expressions are globally static expressions, in + which case the index range of the aggregate is the index range of + the element subtype of the prefix + -- A slice name whose prefix is one of the members of this list and + whose discrete range is a globally static discrete range, in which + case the index range of the aggregate is the discrete range + -- A function call whose return type mark denotes a globally static + subtype, in which case the index range of the aggregate is the + index range of the subtype denoted by the return type mark + -- A qualified expression or type conversion whose type mark denotes a + globally static subtype, in which case the index range of the + aggregate is the index range of the subtype denoted by the type + mark + -- An expression described in this list and enclosed in parentheses, + in which case the index range of the aggregate is the index range + of the subtype defined for the enclosed expression +[DOC: IEEE Std 1076-2008 VHDL LRM - 9.3.3.3 Array aggregates] + + +vcom Message # 1536: +The syntax of a CASE GENERATE statement requires that the reserved word +GENERATE be followed immediately by the reserved word WHEN, which +denotes the start of the first case generate alternative. There must be +at least one case generate alternative. +[DOC: IEEE Std 1076-2008 VHDL LRM - 11.8 Generate statements] + + +vcom Message # 1537: +If a block configuration appears immediately within a configuration +declaration, then the block specification of that block configuration +shall be an architecture name, and that architecture name shall denote a +design entity body whose interface is defined by the entity declaration +denoted by the entity name of the enclosing configuration declaration. +The nature of the visibility rules for an architecture body at the place +of the block specification in a block configuration for an external block +whose interface is defined by a given entity precludes anything except a +simple name being used to denote the architecture. +[DOC: IEEE Std 1076-2008 VHDL LRM - 3.4.2 Block configuration] + 12.3 Visibility] + + +vcom Message # 1538: +It is an error if, in a given block configuration, more than one +configuration item is defined for the same block or component instance. +[DOC: IEEE Std 1076-2002 VHDL LRM - 1.3.1 Block configuration] + + +vcom Message # 1539: +A non-compliant attempt to merge block configurations (because there +duplicates, see message #1286) has resulted in a block configuration +that has duplicate component configurations in it. + + +vcom Message # 1540: +If a block configuration appears immediately within another block +configuration, then the block specification of the contained block +configuration must be a block statement or generate statement label, and +the label must denote a block statement or generate statement that is +contained immediately within the block denoted by the block +specification of the containing block configuration. +[DOC: IEEE Std 1076-2002 VHDL LRM - 1.3.1 Block configuration] + + +vcom Message # 1541: +If the block specification of a block configuration contains a generate +statement label that denotes an IF GENERATE statement, and if the first +condition after the IF has an alternative label, then it is an error if +the block specification does not contain a generate specification that +is an alternative label. Similarly, if the block specification of a +block configuration contains a generate statement label that denotes a +CASE GENERATE statement, then it is an error if the block specification +does not contain a generate specification that is an alternative label. +[DOC: IEEE Std 1076-2008 VHDL LRM - 3.4.2 Block configuration] + + +vcom Message # 1542: +For VHDL 2002 and earlier, if the block specification of a block +configuration contains a label that denotes a FOR GENERATE statement, +the index specification, if present, must be either a (static) discrete +range or a static expression. +For VHDL 2008, if the block specification of a block configuration +contains a label that denotes a generate statement, the generate +specification, if present, must be one of the following: + [FOR GENERATE] -- a static discrete range or a static expression + [IF GENERATE] -- an alternative label + [CASE GENERATE] -- an alternative label +There are no other possibilities. + + +vcom Message # 1543: +The alternative label specified in the generate specification of a block +specification (in a block configuration) that denotes the label of a +generate statement could not be found in that generate statement. + + +vcom Message # 1544: +For VHDL 2002 and earlier, an index specification in a block +specification is allowed only if the block specification contains a +label that denotes a FOR GENERATE statement. +For VHDL 2008, a generate specification in a block specification is +allowed only if the block specification contains a label that denotes a +FOR GENERATE, an IF/ELSIF/ELSE GENERATE, or a CASE GENERATE statement. +In particular a BLOCK statement label cannot appear in a block +specification that contains an index or generate specification. + + +vcom Message # 1545: +For VHDL 2002 and earlier, an index specification in a block +specification is allowed only if the block specification contains a +label that denotes a FOR GENERATE statement. +For VHDL 2008, a generate specification in a block specification is +allowed only if the block specification contains a label that denotes a +FOR GENERATE, an IF/ELSIF/ELSE GENERATE, or a CASE GENERATE statement. + + +vcom Message # 1546: +If the block specification of a block configuration contains a generate +statement label that denotes a FOR GENERATE statement, and if the block +specification contains a generate specification, then the generate +specification must be either a globally static expression or a globally +static range. + + +vcom Message # 1547: +All possible CASE GENERATE expression values are represented in the set +of choices present in all of the case generate alternatives. The case +generate alternative that has the OTHERS choice can never be the chosen +alternative. +This is for information only as it it not illegal. +[DOC: IEEE Std 1076-2008 VHDL LRM - 11.8 Generate statements] +[DOC: IEEE Std 1076-2008 VHDL LRM - 14.5.3 Generate statements] + + +vcom Message # 1548: +CASE GENERATE statement semantics require that all possible values of +statement expression be represented once (and only once) in the set of +choices. The number of choices present would make this prohibitively +expensive in terms of simulator time and memory usage, so these checks +are not being done. +[DOC: IEEE Std 1076-2008 VHDL LRM - 11.8 Generate statements] + + +vcom Message # 1549: +An actual associated with an array or record port must satisfy the +matching element test. + + +vcom Message # 1550: +An actual associated with an array or record port must satisfy the +matching element test. + + +vcom Message # 1560: +An local expressions are the expression supplied in a port map of either +a configuration specficiation in this design unit or a component configuration +located in a configuration design unit. Usually this caused the component +declaration being different from the entity it is bound to. + + +vcom Message # 1561: +The generic interface list contains an overloaded interface subprogram +declaration. In a generic map aspect corresponding to this generic +list, the language (IEEE Std 1076-2008) does not provide a way to +disambiguate the meaning of a named association element whose formal +part is the name of one of these overloaded interface subprograms. +When the generic map does not include an association element for the +interface subprogram, or when it is associated with OPEN, a named +association element would normally be created internally by the compiler +to facilitate obtaining the interface subprogram default of it; such a +named association element would be ambiguous for the same reason. + + +vcom Message # 1562: +Use the -pedanticerrors switch for strict VHDL +compliance to make this an error. + +This message will be an error with the -pedanticerrors argument. + +vcom Message # 1563: +Use the -pedanticerrors switch for strict VHDL +compliance to make this an error. + +This message will be an error with the -pedanticerrors argument. + +vcom Message # 1564: +Upscope pathnames cannot go higher than the design root. Too many +^. were present in the pathname. + + +vcom Message # 1565: +The object referred to by the specified hierarchical path could not +be found. Check that the pathname is valid. Incorrect syntax such as +invalid use of parentheses may also cause this error. + +This error message can be suppressed or downgraded to a note or warning. + +vcom Message # 1566: +No top level design unit with the specified name was found. +You may need to specificy additional design units on the vsim command line. + +This error message can be suppressed or downgraded to a note or warning. + +vcom Message # 1567: +Since external names denote declared objects, and since subelements of a +declared object are not themselves declared objects, it is not legal to +denote an element of a record object using an external name. +Rather, an external name denoting the declared object (of a record type) +can be used as the prefix of a selected name; the suffix of the selected +name shall denote the element of the record. +[DOC: IEEE Std 1076-2008 VHDL LRM - 6.4.2.1 General] +[DOC: IEEE Std 1076-2008 VHDL LRM - 8.7 External names] + + +vcom Message # 1568: +Since external names denote declared objects, and since subelements of a +declared object are not themselves declared objects, it is not legal to +denote an element of a record object using an external name. +Rather, an external name denoting the declared object (of a record type) +can be used as the prefix of a selected name; the suffix of the selected +name shall denote the element of the record. +[DOC: IEEE Std 1076-2008 VHDL LRM - 6.4.2.1 General] +[DOC: IEEE Std 1076-2008 VHDL LRM - 8.7 External names] + + +vcom Message # 1569: +Since external names denote declared objects, and since subelements of a +declared object are not themselves declared objects, it is not legal to +denote an element of a record object using an external name. +Rather, an external name denoting the declared object (of a record type) +can be used as the prefix of a selected name; the suffix of the selected +name shall denote the element of the record. +[DOC: IEEE Std 1076-2008 VHDL LRM - 6.4.2.1 General] +[DOC: IEEE Std 1076-2008 VHDL LRM - 8.7 External names] + + +vcom Message # 1570: +An indexing expression was present in an external name for a path element +that is not a FOR generate label. + + +vcom Message # 1571: +An element of an external name refers to a FOR GENERATE label. +but no index expression is provided. + + +vcom Message # 1572: +Value specified is not a valid index. + + +vcom Message # 1573: +Value specified is not a valid index. + + +vcom Message # 1574: +Unbound instance have nothing in them so they can't have an refernce into them. + + +vcom Message # 1575: +A VHDL external name can denote only an object declared in the +declarative region of an Entity, an Architecture, a Block statement, a +Generate statement, or a Package declaration. A generic or port of an +Entity can also be denoted. +However, in particular, an external name cannot denote an object +declared in a PROCESS statement or a Subprogram. +[DOC: IEEE Std 1076-2008 VHDL LRM - 8.7 External names] + + +vcom Message # 1576: +VHDL Syntax Error. +The compiler has a unified parser that supports all +revisions of the VHDL and VHDL-AMS languages. +Syntax errors are reported with the next possible token(s) that were +expected and would have been legal syntax in one of those revisions. +Those tokens can therefore include some that are not legal +in the revision the user intended to write. + + +vcom Message # 1577: +Parser Error - Memory Exhuasted. + + +vcom Message # 1578: +Parser Error - cannot back up. + + +vcom Message # 1579: +The name refers to a label of generate statement that does not exist when elaborated. +This can be a zero width FOR generate, an IF generate where no branch is TRUE and +no else is present, or a CASE generate that doesn't have a default and no choices match. + + +vcom Message # 1580: +The name of a parameter in a named parameter list does not match any generics in the VHDL entity +being instantiated. + + +vcom Message # 1581: +The operand types of an operator are check against visible operators +in the scope, and no feasible operator was found. + + +vcom Message # 1582: +The evaluation of a qualified expression evaluates the operand and +checks that its value belongs to the subtype denoted by the type mark. +For array subtypes this means that at each position in the index +constraint, the index ranges must match. +[DOC: IEEE Std 1076-1993 VHDL LRM - 7.3.4 Qualified expressions] + + +vcom Message # 1583: +There is no additional information for this message. + + +vcom Message # 1584: +There is no additional information for this message. + + +vcom Message # 1585: +There is no additional information for this message. + + +vcom Message # 1586: +There is no additional information for this message. + + +vcom Message # 1587: +There is no additional information for this message. + + +vcom Message # 1588: +There is no additional information for this message. + + +vcom Message # 1589: +There is no additional information for this message. + + +vcom Message # 1590: +There is no additional information for this message. + + +vcom Message # 1591: +There is no additional information for this message. + + +vcom Message # 1592: +There is no additional information for this message. + + +vcom Message # 1593: +For VHDL to use a System Verilog package, the package must be compiled with -mixedsvvh. +The VHDL may directly reference the System Verilog package in the VHDL source through a +use clause or selected name. The VHDL source may indirectly reference a System Verliog +package if a System Verilog module is instantiated in VHDL and that module has ports or +parameter of types declared in a System Verilog package. + + +vcom Message # 1594: +It is illegal to call a subprogram before its corresponding body is elaborated. +[DOC: IEEE Std 1076-1993 VHDL LRM - 12.3.1 Elaboration of a declaration] +[DOC: IEEE Std 1076-2008 VHDL LRM - 14.4.2.1 General] + +This error message can be suppressed or downgraded to a note or warning. + +vcom Message # 1595: +It is illegal to call a subprogram before its corresponding body is elaborated. +[DOC: IEEE Std 1076-1993 VHDL LRM - 12.3.1 Elaboration of a declaration] +[DOC: IEEE Std 1076-2008 VHDL LRM - 14.4.2.1 General] + +This message will be an error with the -pedanticerrors argument. + +vcom Message # 1596: +An initialization expression for a constant can only refer to +other objects that have already been elaborated. Furthermore, +if a constant's initialization depends on the value returned +from a function call, all objects referenced in the function +(or subprograms referenced by the function) +must have been elaborated before evaluation of the initialization. +To prevent this error and for elaboration to proceed, use the -reorderDeclElab +option of vcom. Note that the behaviour with -reorderDeclElab is not LRM compliant +and may produce incorrect results in the presence of subprograms with side effects. + + +vcom Message # 1597: +A physical path to the library was given but we can't convert it to +to a valid VHDL logical library name. + + +vcom Message # 1598: +A logical library name could not be mapped to a physical location. +A logical to physical library mapping could not be found in the current +.ini file nor does a directory with the same name as the logical library +exist in the current working directory. + + +vcom Message # 1599: +It is illegal to call a subprogram before its corresponding body is elaborated. +The original error generated(1594) was suppressed to allow for elaboration if possible. +A circular dependency was discovered due to which elaboration is not possible +[DOC: IEEE Std 1076-1993 VHDL LRM - 12.3.1 Elaboration of a declaration] +[DOC: IEEE Std 1076-2008 VHDL LRM - 14.4.2.1 General] + + +vcom Message # 1600: +The number of arguments to a subprogram call, or the argument types +do not match any of the subprograms that are defined. All subprograms with +the matching simple name that are visible at this point are listed along +with their signatures. Note that the signature of a subprogram does not indicate +which arguments have default values. + + +vcom Message # 1601: +The operator specified is overloaded and a unique version of the +operator cannot be determined. In many cases the issue is that the +type of an argument cannot be unique determined by context and a +qualified expression is needed of the form '(). + + +vcom Message # 1602: +The subprogram specified is overloaded and a unique version of the +subprogram cannot be determined. In many cases the issue is that the +type of an argument cannot be unique determined by context and a +qualified expression is needed of the form '(). + + +vcom Message # 1603: +The UNIX shell limit, unlimit, or ulimit commands can be used to adjust the current +stacksize limit within bounds set by your system administrator. + + +vcom Message # 1604: +The number of arguments to a subprogram call, expected return type, or the argument types +do not match any of the subprograms that are defined. All subprograms with +the matching simple name that are visible at this point are listed along +with their signatures. Note that the signature of a subprogram does not indicate +which arguments have default values. + + +vcom Message # 1605: +There are more parameters in the user instance's inherit parameter list than there are on the +VHDL entity that is being instantiated. The extra parameters will be ignored. + + +vcom Message # 1606: +The array aggregate has an element that has an index range that is not +identical to the index range of the target array subtype. This is a pedantic +error because the rules for array aggregates describe this requirement where +a simple matching element test should suffice. + + +vcom Message # 1607: +The array aggregate has an element that has an index range that is not +identical to the index range of the target array subtype. This is a pedantic +error because the rules for array aggregates describe this requirement where +a simple matching element test should suffice. + + +vcom Message # 1608: +Design unit dependencies have changed since the last time this design +unit was compiled. The compiled code for the secondary design unit has been +removed from the target library. Compilation order of source files needs +to be reordered so that the primary design unit is compiled before all of +its secondaries. + + +vcom Message # 1609: +The type used is not fully supported with the option -mixedsvvh. +If you have used the -2008 option, it is possible that a VHDL 2008 type +used is not supported with the option -mixedsvvh. + + +vcom Message # 1610: +During compilation with -autoorder, the compiler has detected that multiple +occurrences of a design unit with the same name and type are being compiled +into the same library. Sometimes this will not cause a problem, because the same +source code is just being recompiled. However, there is the possibility that +different functionality will be compiled. The compiler cannot possibly determine +which version of the source code should be retained within the library. By +default, the last to be compiled will be retained. + + +vcom Message # 1611: +Design unit can be configured from either VHDL configuration or from Verilog configuration. +VHDL configuration will be used instead of Verilog configuration. + + +vcom Message # 1612: +The named data member of the named protected type is being used in an +expression involved in defining the subtype of another data member. +QuestaSim does not support this yet. +Please contact support@model.com. + + +vcom Message # 1613: +The reserved word OPEN is legal only in an array constraint in a subtype +indication, as an actual designator in an association list, and as the +entity aspect in a binding indication. +[DOC: IEEE Std 1076-2008 VHDL LRM - 5.3.2.1 General] +[DOC: IEEE Std 1076-2008 VHDL LRM - 6.5.7.2 General] +[DOC: IEEE Std 1076-2008 VHDL LRM - 7.3.2.2 Entity aspect] + + +vcom Message # 1614: +QuestaSim does not support a VHDL design unit with source text that crosses +file boundaries. + + +vcom Message # 1615: +This warning indicates that an entity, configuration, or other design unit has +already been compiled and that another design unit with the same name is +being compiled now. Only the last so-named design unit will be placed +into the library. + + +vcom Message # 1616: +You may be compiling with the wrong version of VHDL-1076 standard. Versions of VHDL-1076 +prior to 2008 standard do not define this type in the STD.STANDARD package. Additionally, +the -amsstd switch will allow any langauge version of VHDL-1076 to access compatible +digital objects defined in the STD.STANDARD package for the AMS version of VHDL. +You could also just be missing a USE clause. + + +vcom Message # 1617: +Ragged arrays are not allowed in VHDL. + + +vcom Message # 1618: +Ragged arrays are not allowed in VHDL. + + +vcom Message # 1620: +When the rules of [11.3 Process statement] were applied, the sensitivity +list was empty. +IEEE Std 1076-2008, 11.3 Process statement + + +vcom Message # 1621: +IEEE Std 1076-1993, 4.3.2.2 Association lists, line 516: + It is an error if an actual of OPEN is associated with a formal that + is associated individually. An actual of OPEN counts as the single + association allowed for the corresponding formal but does not supply + a constant, signal, or variable (as is appropriate to the object + class of the formal) to the formal. +As a result of this unconstrained ports of mode other than IN cannot be +associated with OPEN because there is no actual to constrain the formal port. +EXAMPLE: + Using the following association list as an example: + ( OPEN, p1 => OPEN, p2(7 downto 0) => OPEN ) + For the associations "OPEN" and "p1 => OPEN", the formals are + associated in whole; therefore the first two OPEN association are + legal whether the first formal and p1 are scalars or composites. + For the association "p2(7 downto 0) => OPEN", the subelements of + the formal are associated individually because of the slice + specification; therefore the OPEN association is not legal even + if the slice encompasses the entire range of p2. + +This message will be an error with the -pedanticerrors argument. + +vcom Message # 1622: +Ragged arrays are not allowed in VHDL. + + +vcom Message # 1623: +Ragged arrays are not allowed in VHDL. + + +vcom Message # 1624: +If the component has not generic declared on it, a component instance of this component with generic +map is illegal, but is treated as a warning by default for backwards compatiblity. The generic map +is ignored complete if message is has a severity of warning or less. + + +vcom Message # 1625: +The value either does not belong to the range defined by the range +constraint of a scalar subtype or is not a legal position number in an +enumeration type. + + +vcom-vlog Message # 1900: +Neither the -refresh nor the -force_refresh option can be used with +either the -qhpro_syminfo or -qspro_syminfo option because the +-qhpro_syminfo/-qspro_syminfo options require the original source +code to be available whereas the -refresh/-force_refresh options do +not. The -qhpro_syminfo/-qspro_syminfo options are ignored when +either -refresh or -force_refresh is specified. + + +vcom-vlog Message # 1901: +The file specified for the OptionFile variable in the modelsim.ini file +could not be found. This is a note that can be ignored if you do not +care about the option file. If you do care about the option file, then +verify that the filename is specified correctly, that the file exists, +and that you have permission to read the file. + + +vcom-vlog Message # 1902: +The specified compiler option is either invalid, requires an argument, +or had an unusable argument. +[DOC: QuestaSim Command Reference - vcom/vlog commands] + +This message will be downgraded to a warning with the -permissive argument. +This error message can be suppressed or downgraded to a note or warning. + +vcom-vlog Message # 1903: +While looking for the end of a comment in the specified file, an end +of file condition was encountered. Verify that the correct file was +specified with the -f option and that the file is in a valid format. + + +vcom-vlog Message # 1904: +There is no additional information for this message. + + +vcom-vlog Message # 1905: +The logical name "work" could not be mapped to a physical path name. +The physical path to the work library can be specified with the compiler +option -work. The default is ./work. +[DOC: QuestaSim Command Reference - vcom command, vlog command] + + +vcom-vlog Message # 1906: +The specified library could not be opened. Verify that the path +exists and that the directory is a valid QuestaSim library. + + +vcom-vlog Message # 1907: +Following -nowarn, an additional argument, representing which category +of warning message to suppress, must be specified. + 1 = Unbound component (VHDL) + 2 = Process without a WAIT statement (VHDL) + 3 = Null range (VHDL) + 4 = No space in physical (e.g. TIME) literal (VHDL) + 5 = Multiple drivers on unresolved signal (VHDL) + 6 = VITAL compliance checks ("-nowarn VitalChecks" also accepted) (VHDL) + 7 = VITAL optimization messages (VHDL) + 8 = Lint warnings (VHDL and Verilog) + 9 = Signal value dependency at elaboration (VHDL) + 10 = VHDL-1993 constructs in VHDL-1987 code (VHDL) + 11 = PSL warnings (VHDL and Verilog) + 12 = Non-LRM compliance to match Cadence behavior (Verilog) + 13 = Constructs that coverage can't handle (VHDL and Verilog) + 14 = Locally static error deferred until run time (VHDL) + 15 = SystemVerilog assertions using local variable (Verilog) +[DOC: QuestaSim Command Reference - vcom command] +[DOC: QuestaSim Command Reference - vlog command] +[DOC: QuestaSim Command Reference - vopt command] + + +vcom-vlog Message # 1908: +For the -nowarn option, the following string can be specified instead +of a number: VitalChecks. This is the same as warning category 6 +as in "-nowarn 6". +Use "verror 1907" to see a list of all the -nowarn categories and the +numbers associated with them. + + +vcom-vlog Message # 1909: +The -gen_xml option cannot determine the proper array bounds when +concatenating arrays that have parameterized bounds. + + +vcom-vlog Message # 1910: +The syntax for the -gen_xml option is: + -gen_xml + +where: + is the name of the interface to be generated + is the name of the file where the results are stored. + +NOTE: Use a single dash to have the results sent to standard out. + + +vcom-vlog Message # 1911: +The "NODEBUG_PORTS" option was used to compile the element. Therefore, +no interface information is available to generate the XML output. + + +vcom-vlog Message # 1912: +An invalid option was specified. This message is controlled by the +setting of [vlog] Show_BadOptionWarning in the modelsim.ini file. + + +vcom-vlog Message # 1913: +Only one of toggle or extended toggle may be used. + + +vcom-vlog Message # 1914: +For the -nodebug option to vcom, the word ports can be specified after an +equal sign. +For example: -nodebug=ports + +For the -nodebug option to vlog, one or more of the following strings can +be specified after an equal sign and separated by a plus sign: + ports + pli +For example: -nodebug=ports+pli + +[DOC: QuestaSim Command Reference - vcom command] +[DOC: QuestaSim Command Reference - vlog command] + + +vcom-vlog Message # 1915: +A problem was encountered while trying to load the specified design unit. +Verify that the specified design unit exists in the specified library and +that file permissions allow access to it. The vdir command can be used to +determine which design units exist in a library. + + +vcom-vlog Message # 1916: +The number of parameters provided within a Verilog instantiation of a +VHDL design unit exceeds the number of generics specified in its entity +declaration. + + +vcom-vlog Message # 1917: +The syntax for the Verilog `pragma directive requires that multiple +pragma expressions be separated by the comma character. +The syntax for the VHDL protect directive requires that multiple +keyword expressions be separated by the comma character. + +This message will be an error with the -pedanticerrors argument. + +vcom-vlog Message # 1918: +The specified optimized design unit cannot be used in this context. + + +vcom-vlog Message # 1919: +The name of the design-unit specified with the -o option to vopt began +with a string that is reserved for internal use. + + +vcom-vlog Message # 1921: +The +opt switch has been supplanted by the vopt tool. Please compile your +files (both VHDL and Verilog) and run "vopt" on the design roots to make +an optimized design to simulate. If you still require using +opt, be sure +to use the -novopt switch when you invoke vsim, or set the "VoptFlow" +variable in your modelsim.ini file to a non-zero value. + + +vcom-vlog Message # 1922: +If this error is encountered please contact QuestaSim support. + + +vcom-vlog Message # 1923: +Use the -pedanticerrors switch for strict VHDL +compliance to make this an error. + +This message will be an error with the -pedanticerrors argument. + +vcom-vlog Message # 1924: +Use the -pedanticerrors switch for strict VHDL +compliance to make this an error. + +This message will be an error with the -pedanticerrors argument. + +vcom-vlog Message # 1925: +Use the -pedanticerrors switch for strict VHDL +compliance to make this an error. + +This message will be an error with the -pedanticerrors argument. + +vcom-vlog Message # 1926: +Use the -pedanticerrors switch for strict VHDL +compliance to make this an error. + +This message will be an error with the -pedanticerrors argument. + +vcom-vlog Message # 1927: +Optimized design names exist in the same namespace as design units and so +cannot be the same as an existing design unit. Choose a name for the +optimized design that is not already being used in the library into which +the design is being compiled. The vdir command can be used to find out +which names are being used in the library. + + +vcom-vlog Message # 1928: +A design name must be specified to vopt with the -o switch. + + +vcom-vlog Message # 1929: +PSL 'inherit' is supported only with vopt. + + +vcom-vlog Message # 1930: +Optimized design names may not include mixed case, non-alphanumeric characters +and in certain cases cannot exceed certain name lengths. The optimized design +name supplied violated one of these restrictions. + + +vcom-vlog Message # 1931: +A design-unit referenced by the design being optimized was not found. Either +the library does not exist, or the given entry was not found in the library. +Use the "vdir" command to verify the library and its contents. + + +vcom-vlog Message # 1932: +The "Depends On:" property for a design-unit has been corrupted somehow. +Rebuilding the QuestaSim libraries should fix the problem. + + +vcom-vlog Message # 1933: +The various tools need to use temporary files when performing their function. +These files are created in the current "work" library underneath a directory +named "_temp". This directory was unable to be created for some reason. + + +vcom-vlog Message # 1934: +The various tools need to use temporary files when performing their function. +These files are created in the current "work" library underneath a directory +named "_temp". An attempt was made with the "mkstemp" system call to make +such a file, however the call failed for some reason. + + +vcom-vlog Message # 1935: +An error occurred when a compiler temporary file was attempted to be moved to +another location. + + +vcom-vlog Message # 1936: +An error occurred when a compiler temporary file was attempted to be removed. +(Normally this file may be safely removed by hand if this error occurs.) + + +vcom-vlog Message # 1937: +Use the -pedanticerrors switch for strict VHDL +compliance to make this an error. + +This message will be an error with the -pedanticerrors argument. + +vcom-vlog Message # 1938: +The SDF compiler "sdfcom" could not be found in the installation directory. +Please verify the software has been installed properly. + + +vcom-vlog Message # 1939: +The SDF compiler "sdfcom" was invoked to compile an SDF file referenced +in the design hierarchy and failed for some reason. The transcript of +the compiler should contain the errors indicating what the problem was. + + +vcom-vlog Message # 1940: +When parsing an index value in parentheses or square brackets, a bad +value was seen. + + +vcom-vlog Message # 1941: +When parsing an index in parentheses or square brackets, extra values +were found after the index value was parsed. + + +vcom-vlog Message # 1942: +Extra characters were found after parsing an extended identifier, or an +index or range in parentheses or square brackets. + + +vcom-vlog Message # 1943: +This message is issued when the pathname given to the -sdf{min|typ|max} +switch, indicating the SDF annotation point in the design hierarchy, +either could not be found or is at or inside a PDU region boundary. +In the case of a PDU region, since vopt doesn't load the region under a PDU, +SDF cannot be processed. By design PDUs are expected to have been created +with an SDF file specified to vopt or be annotated in vsim. + + +vcom-vlog Message # 1944: +The pathname given to the -sdf{min|typ|max} switch, indicating where +to apply the SDF to in the design hierarchy, resolved to some other +type of object instead of an instance. + + +vcom-vlog Message # 1945: +The specified compiler option is either invalid or requires an +argument to be specified with it. +If the option is an intended runtime option for vsim specify the option with -R. +[DOC: QuestaSim Command Reference - qverilog command] + +This message will be downgraded to a warning with the -permissive argument. +This error message can be suppressed or downgraded to a note or warning. + +vcom-vlog Message # 1946: +A pathname specified in the SDF file could not be found at the level +of the design hierarchy at which the SDF annotation is being applied. +Verify that the SDF file is being applied at the correct level of the +design. + + +vcom-vlog Message # 1947: +Prints information about recognized FSM's during compile time. + + +vcom-vlog Message # 1948: +The SDF file specified is attempting to annotate to VHDL instances. +Using compiled SDF in this manner is unsupported in the current version +of the simulator. To apply SDF to VHDL you should use the normal +options on vsim (e.g. -sdftyp) to apply the SDF, and remove the usage +of those switches in vopt + + +vcom-vlog Message # 1949: +SystemVerilog compilation must be one of multi-file compilation unit +semantics or single file per compilation unit semantics. + + +vcom-vlog Message # 1950: +The -pdu/-bbox option allows you to specify an optimized design to replace +the instantiation of an individual design-unit in the simulation design +hierarchy. Specifying multiple roots for this type of replacement does +not make sense. + + +vcom-vlog Message # 1951: +The property indicating that the given design-unit should be made a +Preoptimized Design Unit was unable to be added for some unknown reason. + + +vcom-vlog Message # 1952: +The acc option syntax is common for all HDL compilers. It is: + +acc[=][{+[()][.]}] + +acc[=][{+[.]}] +The noacc option syntax is similar to acc option syntax. It is: + +noacc[=][{+[()][.]}] + +noacc[=][{+[.]}] +This syntax is shared with other options such as +floatparameters. +See documentation for further details. + +This error message can be suppressed or downgraded to a note or warning. + +vcom-vlog Message # 1953: +An invalid spec character was specified with the +acc/+noacc option. +The valid spec characters are: + a Enable access to SVA and PSL assertion and cover objects + b Enable access to bits of vector nets + c Enable access to library cells + f Enable fsm recognition and debugging + l Enable access to line debugging + m Enable access to primitives from driving nets + n Enable access to nets + p Enable access to ports + r Enable access to registers, memories, parameters, and variables + s Enable access to system tasks (and overriding of built-ins) + t Enable access to tasks and functions + u Enable access to primitive instances + v Enable access to variables, constants, and aliases in VHDL processes + +When no valid characters are specified, the entire set of access +specifiers is enabled. + +Usage of +acc/+noacc option is as follows. ++[no]acc[=][+[+|.]] + +[DOC: QuestaSim Command Reference - vcom,vlog,and/or vopt commands] + + +vcom-vlog Message # 1954: +A design pathname in a Signal Spy call could not be resolved during the +optimization phase (vopt). +There are 3 possible scenarios: + 1) The pathname itself could not be evaluated by vopt. + The pathname may be an expression of such a complex nature that + vopt could not evaluate it. This warning message will show the + value "" in this case. Passing the "-complexgeneric" + switch to vopt may help to overcome this. + 2) The pathname does not in fact designate an object in the design. + This will always cause vsim to issue the error message #3569. + Check that the designated object does in fact exist. + 3) The pathname does in fact designate some object in the design, but + vopt for some reason could not find it. + +In cases 1 and 3, the object remains subject to being removed from the +design by certain optimizations that vopt applies. +During simulation, if the name does not denote an object in the design +(as in case 2), or if the name denotes an object that has in fact been +removed from the design by vopt (as could happen in cases 1 and 3), then +the Signal Spy call will produce an error message stating that the +object could not be found. If vopt had been able to resolve and find +the object, it would have been preserved during optimization and thus +would have been available to Signal Spy during simulation. Case 2 is an +error no matter what, but cases 1 and 3 may be solved by setting the +"+acc" option on the object to prevent it from being optimized away. + + +vcom-vlog Message # 1955: +The -pdusavehierrefs/-save_bbox_hier_refs/-pduspec/-reporthrefs switch +was specified to 'vopt', but the data file could not be saved. +(The temporary file specified in the error message may still contain the +output information.) + + +vcom-vlog Message # 1956: +An invalid value was specified. Value cannot be less than 32 or more than 1023. + + +vcom-vlog Message # 1957: +Unclocked assertions cannot be simulated. The error cannot be suppressed. +Fix the assertion or comment it out if you are sure you don't need to simulate it. + +This message will be an error with the -pedanticerrors argument. + +vcom-vlog Message # 1958: +The +initmem/+initreg option is: ++initreg[=][+0|1|X|Z][{+[.]}] ++initmem[=][+0|1|X|Z][{+[.]}] +The +noinitmem/+noinitreg option is: ++noinitreg[{+[.]}] ++noinitmem[{+[.]}] +See documentation for further details. + +This error message can be suppressed or downgraded to a note or warning. + +vcom-vlog Message # 1959: +An invalid spec character was specified with the +initreg/+initmem option. +The valid spec characters are: + b Enable initialization of bits and 2-state types + r Enable initialization of reg/logic and 4-state types + e Enable initialization of enumerated types (base type needs to be enabled) + u Enable initialization of sequential udp (valid only for +initreg) +When specified to +initmem, initialization of arrays of these types is enabled. +[DOC: QuestaSim Command Reference - vlog and/or vopt commands] + + +vcom-vlog Message # 1960: +Check +initreg/+initmem options. + + +vcom-vlog Message # 1961: +An implicit optimized design was unable to be created in the current +work library. Normally several errors indicating the problem will +precede this one in the transcript. + + +vcom-vlog Message # 1962: +An implicit optimized design cannot be created in the specified library +due to the fact the directory does not have write permissions. To use +a library without write access, you must simulate a design that has +already been created with vopt, or you must use the -novopt switch when +the design is compiled and simulated. + + +vcom-vlog Message # 1963: +An implicitly named optimized design has been *explicitly* invoked upon +in vsim (e.g. "vsim _opt"). This is allowed, but not recommended due +to the fact that the optimized design will not be locked, and another user +of the current work library might overwrite it if they invoke vsim, and it +implicitly runs vopt. If an optimized design is going to be explicitly +invoked upon, it is much better to run vopt, and use the "-o" option to +give it a more permanent name. + + +vcom-vlog Message # 1964: +In certain cases vsim creates a lock file before vopt is run, or vopt will +create a lock file after vsim invokes it. This lock file is associated +with the implicitly created optimized design, and will typically have a +name like "_opt__lock". However, due to some problem in the system, the +lock file was not created appropriately. + + +vcom-vlog Message # 1965: +The number of partitions requested should be at least 2 and should not exceed 255. + + +vcom-vlog Message # 1966: +The number of CPU's should be one or more. + + +vcom-vlog Message # 1967: +The number of cores per CPU should be one or more. + + +vcom-vlog Message # 1968: +All partitions should have different names. + + +vcom-vlog Message # 1969: +Partition top should be used in only one partition. + + +vcom-vlog Message # 1970: +Synchronization event should exist in the design. + + +vcom-vlog Message # 1971: +Each partition top specified for each partition needs to represent a valid part of the design. +Either partition top is not found in the design or partition top is not a user instance scope. +Partitions cannot be cut at other scopes like block, generate, udp, SystemC instance etc. +Nested SystemC-HDL scope cannot be used. Partitions cannot be empty + + +vcom-vlog Message # 1972: +Partition file should be a readable file. + + +vcom-vlog Message # 1973: +Partition file should conform to proper syntax. + + +vcom-vlog Message # 1974: +Failed to invoke vopt. This message might be followed +by another message that gives more information about the problem. + + +vcom-vlog Message # 1975: +vopt did not finish successfully. This message might be followed +by another message that gives more information about the problem. + + +vcom-vlog Message # 1976: +The -pdu/-bbx option allows you to specify an optimized design to replace +the instantiation of an individual design-unit in the simulation design +hierarchy. However if you do this, the preoptimized design unit +must be written to the same library as the root design unit that is being +replaced. + + +vcom-vlog Message # 1977: +The number of overpartitions requested should be one or more. + + +vcom-vlog Message # 1978: +When refreshing using "vopt" an optimized design-unit name must be +explicitly specified with the -o option. Refreshing all of the optimized +designs-units in a library is not currently supported. + + +vcom-vlog Message # 1979: +When refreshing using the "vopt" tool, command-line options are obtained +from the original creation of the optimized design. Any changed, or additional +options specified on the command-line along with -refresh are ignored. + + +vcom-vlog Message # 1980: +The optimized design that is being refreshed contains insufficient +information to perform the refresh. Normally this is due to attempting +to refresh an older version that did not support it. + + +vcom-vlog Message # 1981: +You cannot refresh separate design-units in an optimized design unless +all the individual pieces are compiled with the same versions of vopt. + + +vcom-vlog Message # 1982: +The design-unit supplied to "vopt" with the -refresh option does not +exist, or is not an optimized design. + + +vcom-vlog Message # 1983: +The optimized design being refreshed has non-Verilog elements in it (e.g. VHDL) +Currently refreshing these designs is not supported. + + +vcom-vlog Message # 1984: +The optimized design being refreshed has elements in it that were compiled with +the "-pslfile_vl" switch. Currently refreshing these designs is not supported. + + +vcom-vlog Message # 1985: +Procedural assign statements with left-hand-side targets across +partition boundary are currently not supported. + + +vcom-vlog Message # 1986: +Nets which cross partition boundaries must have compatible net types +throughout the design hierarchy. Module port connections which join +incompatible nets may result in an error or unexpected results. + + +vcom-vlog Message # 1987: +The vopt "-ka" option was specified, but vopt detected there was some problem, +typically with the compatibility of the previously compiled alternate version +of the optimized design. The error message should contain more information about +what the actual issue is. + + +vcom-vlog Message # 1988: +Each partition name can be used only once in each partition file. + + +vcom-vlog Message # 1989: +Each partition file should have a master partition. + + +vcom-vlog Message # 1990: +Partition name must not contain uppercase characters. + + +vcom-vlog Message # 1991: +Compilation cannot proceed because the target library has been locked. +Use the vlib command to remove the lock. + + +vcom-vlog Message # 1992: +Compilation cannot proceed because the design unit has been locked. +Use the vlib command to remove the lock. + + +vcom-vlog Message # 1993: +Each top-level design unit must be a top of any partition. + + +vcom-vlog Message # 1994: +Option "-equivpack" has not been used correctly. Correct usage is + -equivpack filename +The equivalent package is placed in the named file. + + +vcom-vlog Message # 1995: +The specified package is not usable. This usually happens +due to the usage of unsupported types at mixed language boundary. + + +vcom-vlog Message # 1996: +The specified type is not supported at the SV-VHDL mixed language boundary. +Please refer to Reference Manual for the list of supported types. + + +vcom-vlog Message # 1997: +The expectation of this error is that a VHDL Configuration being compiled +by vcom has encountered a VHDL-AMS design unit. If this is the case then +the user needs to compile the Configuration with the VHDL-AMS compiler. + + +vcom-vlog Message # 1998: +Parallel simulator compiler was unable to determine the absolute pathname for +the partition file. This may cause errors if the simulation is run from a different +directory than where parallel simulation compilation was done. + + +vcom-vlog Message # 1999: +Interface directory is generated by parallel simulation partitioning analysis. +Absence of this directory for given optimized design indicates that either partitioning +analysis has not been done, or optimized design has been over-written. + + +vcom-vlog Message # 2000: +Partitions must not have partition tops that are in the subhierarchy of each other. + + +vcom-vlog Message # 2001: +Usage of the specified option for number of jobs cannot be specified +together with host file. The hostfile can be used to limit the number +of the vopt processes run on each host. + + +vcom-vlog Message # 2002: +Use the -pedanticerrors switch for strict VHDL +compliance to make this an error. + +This message will be an error with the -pedanticerrors argument. + +vcom-vlog Message # 2003: +A package that was earlier compiled with -mixedsvvh option is being +re-compiled without -mixedsvvh option. This will make the package unusable +at the SV-VHDL mixed-language boundary. To use this package at the SV-VHDL +mixed-language boundary, it should be re-compiled with -mixedsvvh option. + + +vcom-vlog Message # 2004: +The +cover option is: ++cover[=][{+[.]}] +The +nocover option is: ++nocover[=][{+[.]}] +See documentation for further details. + +This error message can be suppressed or downgraded to a note or warning. + +vcom-vlog Message # 2005: +An invalid spec character was specified with the +cover or +nocover option. +The valid spec characters are: + b Collect branch statistics + c Collect condition statistics + e Collect expression statistics + f Collect finite machine statistics + s Collect statement statistics + t Collect toggle statistics (Cannot be used with x option) + x Collect extended toggle statistics (Cannot be used with t option) +[DOC: QuestaSim Command Reference - vlog and/or vopt commands] + + +vcom-vlog Message # 2006: +Only one of toggle or extended toggle may be used. If both options are +specified, extended toggle option is selected. + + +vcom-vlog Message # 2007: +Only one of toggle or extended toggle may be used. If both options are +specified, extended toggle option is selected. + + +vcom-vlog Message # 2008: +No module or instance could be found in the design matching the name +specified with the +cover or +nocover option. This name needs to be +a valid scope. +[DOC: QuestaSim Command Reference - vlog/vopt command] + + +vcom-vlog Message # 2009: +Use vdir -l command to find such design units. + + +vcom-vlog Message # 2010: +A partition file must be given after -partfile option. + + +vcom-vlog Message # 2011: +This parameter is either floated by user, or it's cross-partition value is +not fixed during partitioning. Parallel simulation run will not be able to get +correct value during elaboration. You will need to re-partition the design to avoid +cross-partition reference of this parameter. + + +vcom-vlog Message # 2012: +This datatype is currently not supported at partition boundaries. + + +vcom-vlog Message # 2013: +Auto partitioning with VHDL hierarchy is not supported yet. + + +vcom-vlog Message # 2014: +Design cannot be partitioned at VHDL boundary yet. + + +vcom-vlog Message # 2015: +Usage of memory across partition boundary is supported only as global shared memory. +User needs to disable it by specifying proper options, if thats not required. + + +vcom-vlog Message # 2016: +The specified constant is not supported at the SV-VHDL mixed language boundary. +Please refer to Reference Manual for the list of supported types. + + +vcom-vlog Message # 2017: +UPF file name must be specified to vopt with the -pa_upf or -pa_upflist switch. + + +vcom-vlog Message # 2018: +The partition boundary must not have any port connection that are +complex data types, such as interface or instance. + + +vcom-vlog Message # 2019: +There is no additional information for this message. + + +vcom-vlog Message # 2020: +A partition file containing both VHDL and Verilog boundaries is not allowed yet. + + +vcom-vlog Message # 2021: +Design cannot be partitioned at Mixed Language boundary yet. + + +vcom-vlog Message # 2022: +The partition hierarchy cannot have the following vhdl generate block. +Currently we do not support partition of a design below vhdl generates. + + +vcom-vlog Message # 2023: +The partition hierarchy cannot have the following verilog generate block. +Currently we do not support partition of a design below verilog generates. + + +vcom-vlog Message # 2024: +Partition boundary can only be at an user instance scope. Partitions can +not be cut at other scopes like block, generate, udp, SystemC instance etc. +SystemC instance cannot be a design top. +Nested SystemC-HDL scope cannot be used. Partitions cannot be empty + + +vcom-vlog Message # 2025: +Partition instances form a loop that cannot be supported. + + +vcom-vlog Message # 2026: +Partition instances form a loop that cannot be supported. + + +vcom-vlog Message # 2027: +Please check that you have specified correct combination of options. + + +vcom-vlog Message # 2028: +Hierarchical reference object should have known size at Vopt time. +If size depends on parameter and parameter is floated, then size will be unknown. + + +vcom-vlog Message # 2029: +Parallel simulation compiler has encountered an unresolved hierarchical reference. +The object is ignored. This could result in differences in simulation. + + +vcom-vlog Message # 2030: +Preoptimized Design Unit instances must not be located at the partition boundary. + + +vcom-vlog Message # 2031: +An invalid option was specified; this is a fatal error. + + +vcom-vlog Message # 2033: +Specified instances must not be located at the partition boundary. + + +vcom-vlog Message # 2034: +We don't support some configurations in the partition hierarchy. +Try to use a different instance in the partition file. + + +vcom-vlog Message # 2035: +Hierarchical use of mentioned object must be within the same partition. + + +vcom-vlog Message # 2036: +Cross partition usage of mentioned object must be within the same partition. + + +vcom-vlog Message # 2037: +Since partition boundary logic is compiled in SV mode, two of the main +reasons for compilation failures are the presence of a cross-partition +port with a name that is a reserved keyword, and/or the presence of a +hierarchical reference that contains a reserved keyword. +You will need to elminate use of such reserved keywords and recompile. + + +vcom-vlog Message # 2038: +Hierarchical event control triggered by a memory must be within the same partition. + + +vcom-vlog Message # 2039: +Make sure that hierarchical use of unresolved object must be within the same partition, +where this object is declared. Otherwise, it may cause unexpected results later in the flow. + + +vcom-vlog Message # 2040: +The Design unit name specified in partition file should match with, +the design unit name pointed by instance path. + + +vcom-vlog Message # 2041: +Nested instances must not be located at the partition boundary. + + +vcom-vlog Message # 2042: +User-specified partition name cannot be the reserved word "unicore". +Change the partition name to something else. + + +vcom-vlog Message # 2043: +For using parallel simulation, libraries should be properly mapped. +Please make required changes in the modelsim.ini to point it to parallel +simulation library. + + +vcom-vlog Message # 2044: +Check if the profile database exists and if it has valid profile information +by opening database and generating report in vsim. + + +vcom-vlog Message # 2045: +The specified localparam is not supported at the SV-VHDL mixed language boundary. +Please refer to Reference Manual for the list of supported types. + + +vcom-vlog Message # 2046: +All the objects and constructs in directive's expression should be +clocked. LRM forbids such un-clocked objects/constructs. + + +vcom-vlog Message # 2047: +Multi-clocked properties cannot be instanced as top-level (maximal) +property of a directive. + + +vcom-vlog Message # 2048: +Directive cannot have multiple semantic leading clocks. + + +vcom-vlog Message # 2049: +Properties with multiple leading clocks cannot be instanced. + + +vcom-vlog Message # 2050: +The LRM section 'Multiclock support' of SVA requires both sides +of cycle delay operator '##' to be multiply clocked if any one +side is multiply clocked. + + +vcom-vlog Message # 2051: +Coverage, synthesis, and translate off pragmas work on design-unit scope +in VHDL and on file scope in Verilog. These pragmas are reset at the +end of the design-unit and the file respectively. This message occurs +when a coverage, synthesis, or translate off pragma was still in effect +at the end of design-unit or file. Please make sure it is intended. + + +vcom-vlog Message # 2052: +Specified pragma will not be considered. + + +vcom-vlog Message # 2053: +Option "-writetoplevels" has not been used correctly. Correct usage is + -writetoplevels +All the top level modules compiled by the vlog command will be recorded in a +file named . Any previous contents of this file will be over-written. + + +vcom-vlog Message # 2054: +A directory name was found in a context where a file name was expected. + + +vcom-vlog Message # 2055: +The -64 and -32 option requires the necessary executables to be available. +Avoid using these options if the necessary executables are not available. + + +vcom-vlog Message # 2056: +Encrypting parts of composite data types (e.g. struct, class, record) +is not supported. The results are indeterminate. Ostensibly encrypted +fields/elements might not actually be protected. + + +vcom-vlog Message # 2057: +There is no additional information for this message. + + +vcom-vlog Message # 2058: +Repartition to locate all $random uses to a single partition +Or replace $random with $urandom in the original design. + + +vcom-vlog Message # 2059: +A valid recursion level is a number within range 0 to 254, where level 0 indicates +full recursion. + + +vcom-vlog Message # 2060: +Recursion level is applied only if explicit design unit or instance name is specified. +The recursion level is ignored in this case. + + +vcom-vlog Message # 2061: +Parallel simulator autopartitioner could not generate requested number of partitions. +The generated partition file will contain fewer partitions. + + +vcom-vlog Message # 2062: +There were errors when the given file copying process executed. +The log file should contain more details on the errors. + + +vcom-vlog Message # 2063: +Coverage, synthesis, and translate off pragmas work on design-unit scope +in VHDL and on file scope in Verilog. These pragmas are reset at the +end of the design-unit and the file respectively. This message occurs +when a coverage, synthesis, or translate off pragma was still in effect +at the end of design-unit or file. Please make sure it is intended. + + +vcom-vlog Message # 2064: +There were errors during "vopt" code generation for a portion of the design +being compiled. The transcript preceding this message should contain more +details on the failure(s). + + +vcom-vlog Message # 2065: +Instance has been specified multiple times in partitition file + + +vcom-vlog Message # 2066: +The -pdu/-bbox option was specified with a Verilog package as the top-level. +Most likely scenario is that the top-level was compiled with vlog -cuname +and -mfcu options. + + +vcom-vlog Message # 2067: +The access option syntax is : + -access=[[-]]+ +See documentation for further details. + +This error message can be suppressed or downgraded to a note or warning. + +vcom-vlog Message # 2068: +An invalid code character was specified with the -access option. +The valid access code characters specified with -access= are: + r read + w write + c connectivity + - negate the following access code character +When no valid code characters are specified, the default set of code +characters are selected. + + +vcom-vlog Message # 2069: +The -tbxhvllint switch causes the compiler to warn about delays found in +the source code that may cause synchronization issues in Veloce TBX. + + +vcom-vlog Message # 2070: +An existing design unit is being recompiled, and the protected status of +it is being changed. + + +vcom-vlog Message # 2071: +The 'coverage on' pragma does not support nested behavior. +It turns on coverage irrespective of any number of +'coverage off' pragmas encountered earlier in the file. +This message alerts the user with information to check +if code coverage is accidentally being turned 'on'. + + +vcom-vlog Message # 2072: +In a mixed design, if an instance name is a VHDL extended identifier +with white space (\vh dl\) embedded, partitioning at the Verilog/SV +boundary below such instances is not allowed. User can partition at the +VHDL boundary below such instances in these scenario. + + +vcom-vlog Message # 2073: +The tool could not find a suitable library as specified via a 'library_binding' attribute. +Please verify that the library specified by the 'library_binding' attribute is in the +-L library list. +This error is supressible. When this error is suppressed the tool may use +a design element from another library if it can find one. + +This error message can be suppressed or downgraded to a note or warning. + +vcom-vlog Message # 2074: +There were errors when the given tree deletion process executed. +The log file should contain more details on the errors. + + +vcom-vlog Message # 2075: +The "-refresh_dufile" option to specify a file containing a list of design-units +to be refreshed is only applicable if the -refresh option is specified as well. + + +vcom-vlog Message # 2076: +The given "-refresh_dufile" file had an entry on the specified line that could +not be parsed. + + +vcom-vlog Message # 2077: +The given "-refresh_dufile" file had no valid design-unit names in it. + + +vcom-vlog Message # 2078: +There were errors while copying files with debug information while vopt was +doing its compilation. These files are typically not be required for the +design to be simulated correctly, so these errors are being treated as warnings +only. The transcript should contain more information as to the copies that +failed, and the reason for the failure. + + +vcom-vlog Message # 2079: +Rerun parallel simulator partitioning analysis if their is change in partition file. + + +vcom-vlog Message # 2080: +The syntax for the -gen_entity option is: + -gen_entity + +where: + is the name of the interface to be generated + is the name of the file where the results are stored. + + +vcom-vlog Message # 2081: +The syntax for the -gen_dbs option is: + -gen_dbs + + +vcom-vlog Message # 2082: +Cross-partition hierarchical references to variable bit-/part- selects is not supported. + + +vcom-vlog Message # 2083: +Valid new line constructs are formed by either the ASCII character +0x0A or by the ASCII sequence 0x0D 0x0A. This message indicates that +the ASCII character 0x0D was found in the source by itself. The +character 0x0D must be followed by 0x0A in order for line numbering +to work properly. If this warning exists then the line numbers in +the GUI will be incorrect. + + +vcom-vlog Message # 2084: +Packages containing any encrypted content cannot be compiled +with -mixedsvvh. Such packages are not supported for sharing +across the SV-VHDL language boundary. + + +vcom-vlog Message # 2085: +A synthesis off region was detected and its contents are being ignored. +Errors might result from incomplete and/or erroneous representation of the +remaining HDL; the remaining token stream might not represent a legal and +syntactically valid sequence of lexical elements, or dependencies might not +satisfy requirements and assumptions of their users. + + +vcom-vlog Message # 2086: +Auto-partitioner could not annotate the design instnaces with the profile data. +Check if the profile database has valid information by opening the database +and generating report in vsim + + +vcom-vlog Message # 2087: +An invalid option was specified with the -xprop switch. + + +vcom-vlog Message # 2088: +The xprop option syntax is : + -xprop[,mode=][,report=][,object=] +See documentation for further details. + + +vcom-vlog Message # 2089: +Xprop is currently not supported with Parallel Simulation and Coverage. + + +vcom-vlog Message # 2090: +Xprop can be run on instances and modules only. + + +vcom-vlog Message # 2091: +The Module cannot be used as common module. +Please check relevant parallel simulation documentation for further details. + + +vcom-vlog Message # 2092: +Partitioning below common module is not allowed. + + +vcom-vlog Message # 2093: +Please check relevant parallel simulation documentation for further details. + + +vcom-vlog Message # 2094: +Please check relevant parallel simulation documentation for further details. + + +vcom-vlog Message # 2095: +A syntax error occurred in "-pduspec" or "-reporthrefs" specification. +Valid syntax is: +-pduspec+{[] | [[.]]}[+facc=] +-reporthrefs+{[] | [[.]]}[+f=] +Examples: + vopt -pduspec+mymod+facc=mymod.acc ...> + vopt -pduspec+/top/dut1+facc=dut1.acc -pduspec+/top/dut2+facc=dut2.acc ... + vopt -reporthrefs+mymod+f=mymodTbxHierrefs.txt ... + vopt -reporthrefs+/top/dut1+f=dut1TbxHRefs.txt -reporthrefs+/top/dut2+f=dut2TbxHRefs.txt ... +See documentation for further details. + + +vcom-vlog Message # 2096: +-optuvminfo= option will optimize uvm_info and uvm_report_info +messages with higher than given verbosity. Once they are optimized, they +cannot be enabled by changing verbosity at runtime. + + +vcom-vlog Message # 2097: +The 10.3 release no longer supports -fast compiled modules. +Libraries containing -fast design units are refreshed without -fast +and should be optimized using vopt to provide equivalent performance. +[DOC: QuestaSim User's Manual - Optimizing Designs with vopt] + + +vcom-vlog Message # 2098: +Cross-partition usage of a memory can result in incorrect simulation results +when this memory is used as port in design. + + +vcom-vlog Message # 2099: +Check option syntax. See documentation for further details. + + +vlog Message # 2100: +An error was encountered while trying to create a directory. +This message can be issued for a uselib directory specified either by the +-compile_uselibs option or by the environment variable MTI_USELIB_DIR; +it can also come from the encryption tools vencrypt/vhencrypt when the output +directory cannot be created. +Verify that you have write permission in the location where the directory is +to be created. This message might be followed by another message that gives +more information about the problem. + + +vlog Message # 2101: +A `uselib directive must refer to a directory, a file, or a library +extension. For example: + `uselib dir= + `uselib file= + `uselib libext= +[DOC: QuestaSim User's Manual - Verilog chapter] + + +vlog Message # 2102: +The -timescale option takes one argument in the following format: + / +The format for and is the following: + +The value of must be 1, 10, or 100. +The value of must be fs, ps, ns, us, ms, or s. +In addition, the must be greater than or equal +to the . +Example usage: -timescale "1ns / 1ps" +Note that the argument may need to be quoted if it contains +white space. +[DOC: QuestaSim Command Reference - vlog command] + + +vlog Message # 2103: +The directory path specified with the -y option cannot be found. +Make sure that the -y option is specified correctly, that the +directory exists, and that you have read/execute permission for +the directory. Also make sure that any environment variables used in +the -y option are defined and set to the correct values. +[DOC: QuestaSim Command Reference - vlog command] + + +vlog Message # 2104: +The -incrcomp option cannot be specified when either the -incr or the +-noincr option is also specified; the -sv05compat option is also not +allowed. +[DOC: QuestaSim Command Reference - vlog command] + + +vlog Message # 2105: +The -R option was specified but no top-level modules were found in +the design that was just compiled. +[DOC: QuestaSim Command Reference - vlog command] + + +vlog Message # 2106: +While doing a refresh, there was a problem opening the specified +design unit in the specified library. The problem could be one of +the following: + o The library path could not be found. + o The library is not a valid QuestaSim library. + o The design unit was not found in the library. + o The data file for the design unit could not be found or opened. + + +vlog Message # 2107: +Please refer to preceding warnings/errors for more details. + + +vlog Message # 2108: +No module could be found in the design matching the module name +specified with the +acc/-xprop option. +[DOC: QuestaSim Command Reference - vlog command] + + +vlog Message # 2109: +Either the `protected block has been modified after being generated +or it was generated using another vendor's simulation tools. + + +vlog Message # 2110: +The specified object was used in an expression that does not allow that +type of object to be used. + +Example: + +When assigning a value to a net, you cannot use the following type of +assignment statement: + DATA = 2'bzz; +This will result in an "Illegal reference to net" error message. +Instead, if you want to make several assignments to a net, do something +like the following: + reg [31:0] DATAr; + wire [31:0] DATA = DATAr; + initial begin + ... + DATAr = 4'bzzzz; + ... + DATAr = 4'b1100; + ... + end + + +vlog Message # 2111: +A Verilog configuration can contain only one default clause. +For more information on default clause, please refer to : +[DOC: IEEE Std 1800-2012 Verilog LRM - 33.4.1.2 The default clause] + + +vlog Message # 2112: +Library map files were added as part of Verilog 2001 configuration +implementation. A library map file is used to indicate which library a +particular Verilog source description is to be compiled into. Illegal +characters were found in the library path name in a library map file. +Legal characters are all alphanumeric characters, '?', '*', and '.'. + + +vlog Message # 2113: +The library file contains a library pattern that points to a +non-existent physical directory + + +vlog Message # 2114: +The specified file matched more than one library pattern. + + +vlog Message # 2115: +A library map file must be compiled before any Verilog source files to +ensure that all modules are compiled into the correct libraries. A library +map file can be specified anywhere on the command line as long as it is +preceded by the -libmap switch. The -libmap switch is optional if the map +file is the first source file on the command line. Multiple library map +files are allowed, but each one must be preceded by the -libmap switch. + + +vlog Message # 2116: +An environment variable that was used in a configuration library path or +the -incdir include search path was not found in the current environment. + + +vlog Message # 2118: +Constant functions may not contain any hierarchical references, calls +to system functions, or references to identifiers other than functions and +parameters that are defined outside of the function. +[DOC: IEEE Std 1364-2001 Verilog LRM - Section 10.3.5] + + +vlog Message # 2119: +Automatic variables are not allowed as arguments to system tasks like +$monitor, $dumpports and $dumpvar. +[DOC: IEEE Std 1364-2001 Verilog LRM - Section 10.2.3] + + +vlog Message # 2120: +There is no additional information for this message. + +This message will be an error with the -pedanticerrors argument. + +vlog Message # 2121: +Unsized constant numbers shall not be allowed in concatenations. +This is because the size of each operand in the concatenation +is needed to calculate the complete size of the concatenation. +[DOC: IEEE Std 1800-2012 Verilog LRM - 11.4.12 Concatenation operators] + +This message will be an error with the -pedanticerrors argument. + +vlog Message # 2122: +The letter in a display task percent specifier must be one of: + b, c, d, e, f, g, h, l, m, o, s, t, u, v, or z. +To display a literal '%', use '%%'. +[DOC: IEEE Std 1364-2001 Verilog LRM - Section 17.1.1.2] + +This error message can be suppressed or downgraded to a note or warning. + +vlog Message # 2123: +Each percent specifier in a display task format string must correspond +to a subsequent non-null argument. The only exceptions to this are +the %l and %m specifiers. +To display a literal '%', use '%%'. +[DOC: IEEE Std 1364-2001 Verilog LRM - Section 17.1.1] + + +vlog Message # 2124: +Sequence or property when instanced in Clocking Block must have the +same clock as clocking block. + + +vlog Message # 2125: +There is no additional information for this message. + +This message will be an error with the -pedanticerrors argument. + +vlog Message # 2126: +When defining an enum value with the syntax 'name[N:M]' the value for +N and M can be a constant expression with limited references to parameters. +Parameters must be defined in a package and the parameter value must not depend +on any forward references to constant functions. + + +vlog Message # 2127: +The following syntax is illegal: [LRM 1363-2001 Sec 13.3.1.4] + cell lib.cell liblist lib1 lib2; +You must use a USE clause instead of a liblist in this case. + + +vlog Message # 2128: +This implementation follows the draft Verilog 1364-2005 rules for +generate block labels in conditions. Block labels in conditions must +not conflict with other declared names in the enclosing scope and +must not be used in non-nested condition structures, even if those +conditions are never elaborated. + + +vlog Message # 2129: +This note is informative only and is meant to assist +the user in diagnosing design elaboration issues such as +an unexpected large number of loop generated blocks. + + +vlog Message # 2130: +While creating an instance of a system function, it was found that a +system task of the same name was registered either through the PLI or +as a built-in systf. This is an error because the HDL code will expect +the system function to return a value, but the actual system task that +was registered will not do so. + + +vlog Message # 2131: +When defining an enum value with the syntax 'name[N]' the value for +N can be a constant expression with limited references to parameters. +Parameters must be defined in a package and the parameter value must not depend +on any forward references to constant functions. + + +vlog Message # 2132: +This implementation has restricted support for Verilog recursive +instantiations in the default optimized flow. Recursive instantiations +with a VHDL parent or those whose conditions depend on constant function +evaluations are not supported in the optimized flow. Designs with such +constructs must be simulated with the '-incr' switch. + + +vlog Message # 2133: +In order to deal with potentially unbounded recursive instantiations, +this implementation limits the depth of instantiations. The limit +can be modified in your modelsim.ini file if desired. + + +vlog Message # 2134: +In order to deal with potentially unbounded generate for loops, +this implementation limits the number of iterations of a given loop. +The limit can be modified in 'modelsim.ini' if desired. + + +vlog Message # 2135: +More port connections were found in an instantiation than were +expected for the module. + + +vlog Message # 2136: +The second argument to $sdf_annotate() must be an instance path. +Instance paths must end with either no indices or one index, because +Verilog does not allow multi-dimensional arrays of instances. + + +vlog Message # 2137: +There are no generates in path or all the generates are expanded +and hence result in a non-terminating recussion. + + +vlog Message # 2138: +The design unit was found in the library, but it could not be loaded. +Could not open the _primary.dat file in the library directory for the +specified design unit. + + +vlog Message # 2139: +The design unit was found in the library, but it could not be loaded. +The file fast.dat was in the library directory for the specified design +unit. This indicates that the library was probably created with a +version of QuestaSim prior to version 5.5. This is not compatible with +this version of QuestaSim. + + +vlog Message # 2140: +This can occur with a case like this: + covergroup mygroup; + mylabel: coverpoint var1; + mylabel: coverpoint var2; + endgroup +The second 'mylabel' will provoke the error. Because coverpoints are +sometimes named implicitly or named according to the covered variable, +the error may occur in other circumstances, too. + + +vlog Message # 2141: +Automatic or dynamic variables cannot be written with nonblocking +or continuous assignments. Dynamic objects include object handles, +non-static class properties, dynamic and associative arrays, strings, +and event variables. +[DOC: SystemVerilog 3.1a LRM - Section 5.5] + + +vlog Message # 2142: +Only one default skew statement is allow in each clocking block. + + +vlog Message # 2143: +Clocking block identifiers must be declared in the +enclosing scope of the clocking block. + + +vlog Message # 2144: +Coverpoint expressions must be integral. No value in a 'bins' +specification may be unpacked, real, or any other non-integral type. + + +vlog Message # 2145: +Coverpoint expressions must be integral. No value in a 'bins' +specification may be unpacked, real, or any other non-integral type. + + +vlog Message # 2146: +Coverpoint expressions must have integral types. Unpacked types, +reals, and other non-integral types are illegal. + + +vlog Message # 2147: +Expressions in 'bins' size, value or transition specifications must only +refer to constants or covergroup constructor arguments. + +This message will be an error with the -pedanticerrors argument. + +vlog Message # 2148: +IEEE1364[13.3.3] - specify paths without a data source expression are +treated as level-sensitive and cannot contain a from edge. Since the +data source expression is not used by simulation, downgrading of this +error (to a note or warning) causes the specify path to be accepted as +an edge-sensitive path. + + +vlog Message # 2149: +Non-blocking assignments to program block variables are illegal. + + +vlog Message # 2150: +Blocking assignments to hierarchical references in a program block are illegal. + + +vlog Message # 2151: +There is no additional information for this message. + +This message will be an error with the -pedanticerrors argument. + +vlog Message # 2152: +From SystemVerilog LRM P1800 Draft 4, Section 21.3: +Covergroup defined in a Class is called an embedded Covergroup. +Such embedded Covergroups are implicitly of anonymous type and +Class containing this Covergroup has implicit variable with same +name as the embedded Covergroup. Explicit user-defined variables +of the embedded Covergroup types are not allowed. Following syntax +for object creation is only allowed for embedded Covergroup types. + class c; + covergroup ct; + endgroup + ct = new; // really implicit variable named 'ct' of type 'ct' + endclass + + +vlog Message # 2153: +There is no additional information for this message. + + +vlog Message # 2154: +Cannot mark the specified signal as sparse. + + +vlog Message # 2155: +Global declarations are only legal in SystemVerilog. To enable SystemVerilog you +can either use the -sv vlog command line switch or give the source file a .sv +extension. + + +vlog Message # 2156: +default clocking specified multiple times. +[DOC: SystemVerilog 3.1a LRM - Section 15.11] + + +vlog Message # 2157: +default clocking identifier '%s' does not match previously defined default clock '%s'. +[DOC: SystemVerilog 3.1a LRM - Section 15.11] + + +vlog Message # 2158: +Automatic variables are not allowed to be used inside a fork-join_none +or fork-join_any block. + + +vlog Message # 2159: +Unlike native function/task prototypes, other decls require identifiers for formals. + + +vlog Message # 2160: +Clocking block output synchronous drives must use '<=' assignment. +[DOC: IEEE Std 1800-2005 SystemVerilog LRM - Section 15.14] + + +vlog Message # 2161: +On Windows and AIX, it is not allowed to place C/C++ files containing DPI +export tasks and functions on the compiler command line. Instead, compile +the C/C++ code ahead of time, and then use the -R -sv_lib switch +to load the DPI code into the simulator. + + +vlog Message # 2162: +-cuname requires -mfcu on the commandline. + + +vlog Message # 2163: +The compiler directive/macro is not recognized by QuestaSim. If this +error has been generated from within a protected region then contact +the provider of the IP to verify that no references to undefined +macros exist within the protected region. + + +vlog Message # 2164: +Class or package declarations must be compiled before being referenced. + + +vlog Message # 2165: +QuestaSim automatically generates and compiles "glue" code for Systemc +SystemVerilog DPI tasks and functions. The compilation of the generated +code failed. See the error message text for clues to the problem. + + +vlog Message # 2166: +The tool automatically maintains a database for DPI TF instances and types. +Each time a vlog compile will add the TF instances and types from current +compile into the database as new entries. The related operation is failed. + + +vlog Message # 2167: +Protected and local class properties are not yet supported + + +vlog Message # 2168: +A SystemVerilog design with $unit declarations references more than one library. +This may happen when both -libmap and -mfcu are used. + + +vlog Message # 2169: +A SystemVerilog source file within a library directory specified with -y +contains a declaration in $unit scope and the compiler is in mfcu mode. + + +vlog Message # 2170: +A SystemVerilog source file within a library file specified with -v +contains a declaration in $unit scope. + + +vlog Message # 2171: +Multi-clock sequence or property is not allowed in clocking block. + + +vlog Message # 2172: +The dpiheader file cannot be generated if a struct argument has +elements composed of parameterized types or parameterized widths. +Generating the dpiheader file at a later processing stage may help +work around this issue, since parameters become better settled +in later processing stages. + + +vlog Message # 2173: +The P1800-2005 LRM stipulates that C linkage be used for DPI. +Thus identifier names visible on the C side of DPI must be legal +C identifiers. + + +vlog Message # 2174: +If a DPI tf has an anonymous struct argument, the DPI tf cannot +be called due to strong type checking. Use a typedef instead. + + +vlog Message # 2175: +An un-labeled Coverpoint is covering a simple named variable +which exists in Covergroup scope or the user specified label of +Coverpoint is already the name of another object in Covergroup scope. +Thus hindering the creation of Coverpoint variable with same name. + + +vlog Message # 2176: +A SystemVerilog source file within a library file specified with -v +contains a package declaration that will not be compiled. Packages are +ignored during library file scanning. + + +vlog Message # 2177: +There is no additional information for this message. + + +vlog Message # 2178: +QuestaSim automatically maintains a database for all DPI-SC TF instances. +The current database file present in work library was generated by a later +version software and can't be read. Either use a later version software or +run a clean recompile of all the source files using the current software. + + +vlog Message # 2179: +QuestaSim automatically maintains a database for all DPI TF instances. +The current database file present in work library was generated by an older +version software. New DPI features might not be available unless the +relevant source files are recompiled with the current software. + + +vlog Message # 2180: +Passing an array of SystemC Data type objects in DPI-SC call is not currently supported. + + +vlog Message # 2181: +Using a parameterized class without explicit parameters creates a +specialization of the parameterized class using the default parameters. +A parameterized class is not a type; only specializations of the +parameterized class are types. + + +vlog Message # 2182: +The indicated variable in an always_comb or an always @*block might be read before +it is written. In that case, the reader will not see the updated value. + + +vlog Message # 2183: +Due to support for separate compilation, it is not possible to determine +the actual type of a type referenced from an interface. As a result any +references to inherited names must be prefixed by "this." or "super." +in order for the compiler to determine that the references are intended to be +references to members inherited from the final type. + + +vlog Message # 2184: +Due to support for separate compilation, it is not possible to determine +the actual type of a type parameter. When a type parameter is used as +the super class type for a class extension, it is not possible to +determine the inherited property or method names. As a result any references +to inherited names must be prefixed by "this." or "super." in order +for the compiler to determine that the references are intended to be +references to members inherited from the final type. Using a class type +as the default allows the compiler to assume knowledge about members +inherited from the super type. + + +vlog Message # 2185: +This can occur with a case like this: + covergroup mygroup; + mylabel: cross var1, var1; + endgroup +The second 'var1' will provoke the warning since a cross between a +coverpoint or variable and itself produces the same results as the +coverpoint or variable alone. + + +vlog Message # 2186: +This module may not run in the QuestaSim Personal Edition. + + +vlog Message # 2187: +From the Verilog LRM 1364-2005 section 19.11: +Each `begin_keywords directive must be paired with an `end_keywords directive. + + +vlog Message # 2188: +From the Verilog LRM 1364-2005 section 19.11: +Each `begin_keywords directive must be paired with an `end_keywords directive. + + +vlog Message # 2189: +QuestaSim automatically maintains a database for all DPI-SC TF instances. +The current database file present in work library was generated on a different +kind platform. This is incompatible with current platform. The +relevant SV source files need to be recompiled on current platform. + + +vlog Message # 2190: +There is no additional information for this message. + + +vlog Message # 2191: +There is no additional information for this message. + + +vlog Message # 2192: +There is no additional information for this message. + + +vlog Message # 2193: +The design unit that is being bound is either not a supported type, or +is not of a valid type. + + +vlog Message # 2194: +The target of the bind statement is not of valid type. + + +vlog Message # 2195: +Hierarchical reference in actual expression of bind statement not supported +when target of bind is a VHDL design unit. + + +vlog Message # 2196: +This type of expression is not supported when target of bind is VHDL +design unit. Please refer to User Guide for supported expression types. + + +vlog Message # 2197: +'.*' port connection not allowed when target of bind is a VHDL design unit. + + +vlog Message # 2198: +Parameterized value or type is not currently supported in DPI-SC. + + +vlog Message # 2199: +When using a hierarchical expression in a clocking block variable declaration +the variable being declared may not be a hierarchical path. +[DOC: IEEE Std 1800-2005 SystemVerilog LRM - Section 15.4] + + +vlog Message # 2200: +QuestaSim automatically generates and compiles "glue" code for Systemc +SystemVerilog DPI tasks and functions. The generation of the wrapper C++ +code failed. See the error message text for clues to the problem. + + +vlog Message # 2201: +QuestaSim automatically generates "glue" code for each SystemVerilog library +specified by -dpilib switch. However QuestaSim could not find any usage of SystemC +DPI in this library. + + +vlog Message # 2202: +Clocking block variables may not be dynamic array type or string type. +Clocking block output variables may not be of unpacked array type. + + +vlog Message # 2203: +The clocking_event designates a particular event to act as the clock for the clocking block. +The timing used to drive and sample all other signals specified +in a given clocking block is governed by its clocking event. +clocking_event ::= @ identifier | @ ( event_expression ) +[DOC: IEEE Std 1800-2012 Verilog LRM - 14.3 Clocking block declaration] + + +vlog Message # 2204: +The clocking_skew determines how many time units away from the clock event +a signal is to be sampled or driven. Input skews are implicitly negative, that is, +they always refer to a time before the clock, whereas output skews always refer +to a time after the clock. When the clocking event specifies a simple edge, +instead of a number, the skew can be specified as the specific edge of the signal. +[DOC: IEEE Std 1800-2012 Verilog LRM - 14.3 Clocking block declaration] + + +vlog Message # 2205: +The DPI import function can have only the following return types: void, byte, +shortint, int, longint, real, shortreal, chandle, string. +Std 1800-2005 26.4.5 + + +vlog Message # 2206: +There is no additional information for this message. + + +vlog Message # 2207: +There is no additional information for this message. + + +vlog Message # 2208: +There is no additional information for this message. + + +vlog Message # 2209: +There shall be at most one timeUnit/timePrecision in any compilation-unit scope. +These values can be repeated, but they must match. + + +vlog Message # 2210: +There shall be at most one timeUnit/timePrecision in any compilation-unit scope. +Once the default timeUnit/timePrecision is used by one module, another module +cannot set a new value. + + +vlog Message # 2211: +If an import DPI function declares a formal argument (input, inout, or output) +that is a fixed size array, then a dynamic array of the same size can be +passed as an actual argument to this function. However, if the function +declares a formal argument that is an unsized array, a dynamic array of any +size can only be passed to formal arguments of input and inout mode +(not output). Refer to Section 5.8 Arrays as arguments in IEEE Std 1800-2005. + + +vlog Message # 2212: +Clocking block output synchronous drives may only use ## cycle delay. +[DOC: IEEE Std 1800-2005 SystemVerilog LRM - Section 15.14] + + +vlog Message # 2213: +For specifics consult the QuestaSim User's Manual on mixed language simulation. + + +vlog Message # 2214: +For specifics consult the QuestaSim User's Manual on mixed language simulation. + + +vlog Message # 2215: +Option "-mixedsvvh" has not been used correctly. Correct usage is + -mixedsvvh [b|s|v] [packedstruct] + b => generate equivalent bit + s => generate equivalent std_logic + v => generate equivalent vl_logic (default) + packedstruct => map packed struct to VHDL record type + + +vlog Message # 2216: +There is no additional information for this message. + + +vlog Message # 2217: +If a default argument value is specified in the out-of-block declaration, +then there shall be a syntactically identical default argument value specified in the prototype. +[DOC: IEEE Std 1800-2012 Verilog LRM - 8.24 Out-of-block declarations] + +This message will be an error with the -pedanticerrors argument. + +vlog Message # 2218: +There is no additional information for this message. + + +vlog Message # 2219: +There is no additional information for this message. + +This message will be downgraded to a warning with the -permissive argument. +This error message can be suppressed or downgraded to a note or warning. + +vlog Message # 2220: +The value of the specified parameter has been given using the -g or -G +option. The -g/-G option overrides the +floatparameters option. + + +vlog Message # 2221: +There is no additional information for this message. + + +vlog Message # 2222: +If specified, the timeUnit and timePrecision declarations shall precede +any other items in the current time scope. +These values can be repeated, but if they repeate then all repitions +must specify the same value. + + +vlog Message # 2223: +Section 13.6 of the IEEE P1800-2005 LRM specifies that variable names referenced +in an in-line constraint block are first resolved with respect to the scope of the +randomized object class. If a name fails to resolve within that scope, the name +is resolved normally, starting in the scope containing the in-line constraint. +QuestaSim does not currently support resolution of variable names in in-line +constraint blocks, with respect to the scope of the randomized object class, +when a call to class::randomize() is made via a path that cannot be resolved +at compile time (i.e. parameterized class instance or hierarchical instance). + + +vlog Message # 2224: +Clocking block inputs may only be read, not driven. +NOTE: The line number reported may show the first use of the clocking block input, +but the error may be with another occurrence of the clocking block input. + + +vlog Message # 2225: +Clocking block outputs may only be used on the left hand side of a clocking drive '<=' +NOTE: The line number reported may show the first use of the clocking block output, +but the error may be with another occurrence of the clocking block output. + + +vlog Message # 2226: +There is no additional information for this message. + + +vlog Message # 2227: +Constraint Blocks declared within a class need to be defined outside the class. +For Constraint block declaration syntax, please refer to : +[DOC: IEEE Std 1800-2012 Verilog LRM - 18.5 Constraint blocks] + + +vlog Message # 2228: +No module or instance could be found in the design matching the name +specified with the +initmem/+initreg/+noinitmem/+noinitreg option. +This name needs to be a valid scope or a register or a memory name. +The design unit name cannot match with the name of a nested +module/program/interface. +This option cannot be applied to an instance name with nested +module/program/interface hierarchy. +[DOC: QuestaSim Command Reference - vlog/vopt command] + + +vlog Message # 2229: +A SystemC datatype was not used according to the use model. Please refer +to the User's Guide for the correct usage of SystemC datatypes in DPI. + + +vlog Message # 2230: +An alias statement declares multiple names for the same physical net, + or bits within a net. The syntax for an alias statement is as follows: +net_alias ::= alias net_lvalue = net_lvalue { = net_lvalue } ; +net_lvalue ::= + ps_or_hierarchical_net_identifier constant_select + | { net_lvalue { , net_lvalue } } + | [ assignment_pattern_expression_type ] assignment_pattern_net_lvalue +[DOC: IEEE Std 1800-2012 Verilog LRM - 10.11 Net aliasing] + +This error message can be suppressed or downgraded to a note or warning. + +vlog Message # 2231: +Aliasing a reg is not allowed. +For more information on aliasing, please refer to: +[DOC: IEEE Std 1800-2012 Verilog LRM - 10.11 Net aliasing] + + +vlog Message # 2232: +The nets connected with an alias statement must be type compatible, that +is, they have to be of the same net-type. For example, it is illegal to +connect a wand net to a wor net with an alias statement. + + +vlog Message # 2233: +There is no additional information for this message. + + +vlog Message # 2234: +There is no additional information for this message. + + +vlog Message # 2235: +Due to IEEE 1364 PLI requirements, the representation for a memory element +cannot be the same as the representation of a non-memory declaration. +When a memory element is used as the actual for a 'ref' mode formal, +inout semantics must be followed in order to convert the representation. + + +vlog Message # 2236: +A task is not permitted to be called with a void'() cast. Casts are +permitted only with function enables. + + +vlog Message # 2237: +See the QuestaSim Reference Manual for details on usage. + + +vlog Message # 2238: +IEEE Std 1800 does not allow the literal 'null' to be assigned to +a dynamic array. This implementation permits such assignments as +being equivalent to a resize of the array to size 0. + + +vlog Message # 2239: +The compiler has detected a situation in which something that is likely +a function call is being used in a manner such that the return value is +being ignored; thus an implicit VOID cast of the return value is +assumed. It is generally not a good idea to throw away a function +return value. + + +vlog Message # 2240: +The compiler has detected a situation in which a function call is being +used in a manner such that the return value is being ignored; thus an +implicit VOID cast of the return value is assumed. It is generally not +a good idea to throw away a function return value. + + +vlog Message # 2241: +An expression connected to a module instance port has a different +number of bits than the formal port declaration. + + +vlog Message # 2242: +Array with unsized packed or unpacked dimensions is not allowed to be used as + a field of struct when passed as DPI tf argument type. + + +vlog Message # 2243: +Subrouties called in the action block of deferred assertions +can only contain input or ref type of formals. + + +vlog Message # 2244: +An explicit static keyword shall be required when an initialization value +is specified as part of a static variable's declaration to indicate the +user's intent of executing that initialization only once at the beginning +of simulation. The static keyword shall be optional where it would not be +legal to declare the variables as automatic. +[DOC: IEEE Std 1800-2009 Verilog LRM - 6.21 Scope and Lifetime] +Variable initialized in its declaration in a static task, function or +procedural block requires an explicit static keyword. + +This message will be downgraded to a warning with the -permissive argument. +This error message can be suppressed or downgraded to a note or warning. + +vlog Message # 2245: +Type of VHDL hierarchical reference used as actual expression in bind +statement cannot be defined in architecture or package body. Such types +must always be defined in packages visible in target VHDL scopes. + + +vlog Message # 2246: +The specified hierarchical reference is not supported in actual + + +vlog Message # 2247: +The port is bound in the module instantiation using .*. No identifier +with the same name is in scope at the module instantiation location. + +This error message can be suppressed or downgraded to a note or warning. + +vlog Message # 2248: +Re-definition of ANSI style port declaration is allowed with the +-mixedansiports option. This can cause run time errors if the types +do not match. + + +vlog Message # 2249: +There is no additional information for this message. + + +vlog Message # 2250: +The function has a return path in which no return value is being +explicitly set. + + +vlog Message # 2251: +Concatenation of an unpacked value is technically illegal. We allow it +in this case. + +This message will be an error with the -pedanticerrors argument. + +vlog Message # 2252: +Leaving out parts of a 'for' loop is not supported by the BNF at +this time, but we allow it as it is acceptable in 'C'. + +This message will be an error with the -pedanticerrors argument. + +vlog Message # 2253: +Top-level module name must be specified as "" or +"." . + + +vlog Message # 2254: +This module may not run in the QuestaSim Deluxe Edition. + + +vlog Message # 2255: +Event expressions shall return singular values. +Aggregate types can be used in an expression provided the expression +reduces to a singular value. The object members or aggregate elements can be +any type as long as the result of the expression is a singular value. +[DOC: IEEE Std 1800-2012 Verilog LRM - 9.4.2 Event control] + +This error message can be suppressed or downgraded to a note or warning. + +vlog Message # 2256: +The Verilog standard is unclear as to the meaning of aggregate valued +event expressions. This construct is best avoided. + + +vlog Message # 2257: +The identifier after endtask or endfunction cannot be qualified with +a class name. + +This message will be an error with the -pedanticerrors argument. + +vlog Message # 2258: +Either eliminate the label or try to compile the design as a SystemVerilog +design using the -sv switch. + +This error message can be suppressed or downgraded to a note or warning. + +vlog Message # 2259: +Sequence or property when declared in Clocking Block cannot have +clocking events. + + +vlog Message # 2260: +If this is a SystemVerilog design, compile using the -sv switch. + +This message will be an error with the -pedanticerrors argument. + +vlog Message # 2261: +The name provide is to a previously optimized design. Optimized design +cannot be reoptimized. + + +vlog Message # 2262: +The name provide is to a previously optimized design. Optimized design +cannot be reoptimized. + + +vlog Message # 2263: +Macro redefinition. + + +vlog Message # 2264: +Attempt to redefine a compiler directive. +If the command line specified a '-f' argument then carefully look +for command line macro definitions specified in the argument file. +Since a macro may be defined on the command line using plusargs +notation unexpected behavior may result. + + +vlog Message # 2265: +There is no additional information for this message. + + +vlog Message # 2266: +There is no additional information for this message. + + +vlog Message # 2267: +There is no additional information for this message. + + +vlog Message # 2268: +There is no additional information for this message. + + +vlog Message # 2269: +There is no additional information for this message. + + +vlog Message # 2270: +There is no additional information for this message. + + +vlog Message # 2271: +There is no additional information for this message. + + +vlog Message # 2272: +There is no additional information for this message. + + +vlog Message # 2273: +There is no additional information for this message. + + +vlog Message # 2274: +There is no additional information for this message. + + +vlog Message # 2275: +This warning indicates that a module, primitive, or other design unit has +already been compiled and that another design unit with the same name is +being compiled now. Only the last so-named design unit will be placed +into the library. + + +vlog Message # 2276: +There is no additional information for this message. + + +vlog Message # 2277: +IEEE Std 1800 does not allow the parameter specifications to follow +the modport aspect of a virtual interface declaration. +This implementation permits the form 'interface_name.modport #(params)' +which is treated as being equivalent to the IEEE permitted form +'interface_name #(params).modport'. + + +vlog Message # 2278: +The actual and formal types do not match. + + +vlog Message # 2279: +Illegal formal type used in property or sequence expression. +For rules of typed formal arguments in a sequence expression, please refer to: +[DOC: IEEE Std 1800-2012 Verilog LRM - 16.8.1 Typed formal arguments in sequence declarations] + + +vlog Message # 2280: +There is no additional information for this message. + + +vlog Message # 2281: +There is no additional information for this message. + + +vlog Message # 2282: +IEEE Std 1800 does not allow creating cover cross from other crosses. +This implementation permits such coverage construct. + + +vlog Message # 2283: +An isolated semicolon was found in the $unit (global) scope. For +SystemVerilog designs, if no other $unit declarations exist, this +will result in the unnecessary creation of an empty $unit scope. + +This message will be an error with the -pedanticerrors argument. + +vlog Message # 2284: +An empty $unit (global) scope has been created. This is the result +of an extra semicolon in $unit scope. + +This message will be an error with the -pedanticerrors argument. + +vlog Message # 2285: +Concatenation of a real expression is technically illegal. +[DOC: IEEE Std 1800-2012 Verilog LRM - Table 11-1 Operators and data types] + + +vlog Message # 2286: +The specified directory was added to the include file search list. +The directory location was derived from the location of the imported library. + + +vlog Message # 2287: +An included file was found with an unexpected path. Check +incdir+ +locations to ensure compatibility with associated library. + + +vlog Message # 2288: +Check library search order (-Lf and -L) and package compile order. + + +vlog Message # 2289: +Only nonvoid functions with no output or inout arguments can be specified as pure. + +This message will be an error with the -pedanticerrors argument. + +vlog Message # 2290: +Local var formals of type inout and out cannot have default argument. + + +vlog Message # 2291: +A task, a function or another type of declaration has already been made using this name. +A name cannot be declared more than once within a scope. + +This message will be downgraded to a warning with the -permissive argument. +This error message can be suppressed or downgraded to a note or warning. + +vlog Message # 2292: +A file was included from an unexpected location. Check +incdir+ +locations to ensure compatibility with associated library. + + +vlog Message # 2293: +Parameters can be declared without an explicit initial value for vlog. +However a value must be supplied to the parameter during elaboration. + + +vlog Message # 2294: +In a data declaration it shall be illegal to omit the data type before a +list of variable declaration assignments unless the 'var' keyword is used. +This message will be an error in the next minor number release of Questa. +[DOC: IEEE Std 1800-2009 Verilog LRM - Section A.10 "Footnotes (normative)"] + + +vlog Message # 2295: +Within a fork-join_any or fork-join_none block, it shall be illegal to refer to formal +arguments passed by reference other than in the initialization value expression of variables +declared in a block_item_declaration of the fork. +This message is suppressible with static actual arguments. +[DOC: IEEE Std 1800-2009 Verilog LRM - Section 9.3.2 "Parallel blocks"] + + +vlog Message # 2296: +A fixedsize unpacked array, dynamic array, or queue, or a slice of such an array, +shall be assignment compatible with any other such array or slice, +if all the following conditions are satisfied: +- The element types of source and target shall be equivalent. +- If the target is a fixed-size array or a slice, + the source array shall have the same number of elements as the target. +[DOC: IEEE Std 1800-2012 Verilog LRM - 7.6 Array assignments] + + +vlog Message # 2297: +There is no additional information for this message. + + +vlog Message # 2298: +There is no additional information for this message. + + +vlog Message # 2299: +There is no additional information for this message. + + +vlog Message # 2300: +There is no additional information for this message. + + +vlog Message # 2301: +There is no additional information for this message. + + +vlog Message # 2302: +There is no additional information for this message. + + +vlog Message # 2303: +There is no additional information for this message. + + +vlog Message # 2304: +There is no additional information for this message. + + +vlog Message # 2305: +There is no additional information for this message. + + +vlog Message # 2306: +There is no additional information for this message. + + +vlog Message # 2307: +There is no additional information for this message. + + +vlog Message # 2308: +There is no additional information for this message. + + +vlog Message # 2309: +`default_nettype directive syntax: +default_nettype_compiler_directive ::= Default_nettype default_nettype_value +default_nettype_value ::= +wire | tri | tri0 | tri1 | wand | triand | wor | trior | trireg | uwire | none +[DOC: IEEE Std 1800-2012 Verilog LRM - 22.8 `default_nettype] + + +vlog Message # 2310: +The directive `unconnected_drive takes one of two arguments-pull1 or pull0. +When pull1 is specified, all unconnected input ports are automatically pulled up. +When pull0 is specified, unconnected ports are pulled down. +[DOC: IEEE Std 1800-2012 Verilog LRM - 22.9 `unconnected_drive and `nounconnected_drive] + + +vlog Message # 2312: +There is no additional information for this message. + + +vlog Message # 2313: +The syntax for the `timescale directive is +timescale_compiler_directive ::= `timescale time_unit / time_precision +The time_unit argument specifies the unit of measurement for times and delays. +The time_precision argument specifies how delay values are rounded before being used in simulation. +[DOC: IEEE Std 1800-2012 Verilog LRM - 22.7 `timescale] + + +vlog Message # 2314: +Valid uselib arguments are : "dir", "file", "lib", "libnext" + + +vlog Message # 2315: +There is no additional information for this message. + + +vlog Message # 2316: +There is no additional information for this message. + + +vlog Message # 2317: +There is no additional information for this message. + + +vlog Message # 2318: +There is no additional information for this message. + + +vlog Message # 2319: +There is no additional information for this message. + + +vlog Message # 2320: +There is no additional information for this message. + + +vlog Message # 2321: +There is no additional information for this message. + + +vlog Message # 2322: +There is no additional information for this message. + + +vlog Message # 2323: +There is no additional information for this message. + + +vlog Message # 2324: +There is no additional information for this message. + + +vlog Message # 2325: +There is no additional information for this message. + + +vlog Message # 2326: +There is no additional information for this message. + + +vlog Message # 2327: +There is no additional information for this message. + + +vlog Message # 2328: +There is no additional information for this message. + + +vlog Message # 2329: +There is no additional information for this message. + + +vlog Message # 2330: +There is no additional information for this message. + + +vlog Message # 2331: +There is no additional information for this message. + + +vlog Message # 2332: +There is no additional information for this message. + + +vlog Message # 2333: +There is no additional information for this message. + + +vlog Message # 2334: +There is no additional information for this message. + + +vlog Message # 2335: +There is no additional information for this message. + + +vlog Message # 2336: +There is no additional information for this message. + + +vlog Message # 2337: +There is no additional information for this message. + + +vlog Message # 2338: +There is no additional information for this message. + + +vlog Message # 2339: +There is no additional information for this message. + + +vlog Message # 2340: +There is no additional information for this message. + + +vlog Message # 2341: +There is no additional information for this message. + + +vlog Message # 2342: +There is no additional information for this message. + + +vlog Message # 2343: +There is no additional information for this message. + + +vlog Message # 2344: +There is no additional information for this message. + + +vlog Message # 2345: +There is no additional information for this message. + + +vlog Message # 2346: +There is no additional information for this message. + + +vlog Message # 2347: +The PSL formal parameter value can be one of 'bitvector', 'numeric' or 'bit'. + + +vlog Message # 2348: +There is no additional information for this message. + + +vlog Message # 2349: +There is no additional information for this message. + + +vlog Message # 2350: +There is no additional information for this message. + + +vlog Message # 2351: +There is no additional information for this message. + + +vlog Message # 2352: +There is no additional information for this message. + + +vlog Message # 2353: +There is no additional information for this message. + + +vlog Message # 2354: +There is no additional information for this message. + + +vlog Message # 2355: +There is no additional information for this message. + + +vlog Message # 2356: +There is no additional information for this message. + + +vlog Message # 2357: +There is no additional information for this message. + + +vlog Message # 2358: +There is no additional information for this message. + + +vlog Message # 2359: +There is no additional information for this message. + + +vlog Message # 2360: +There is no additional information for this message. + + +vlog Message # 2361: +There is no additional information for this message. + + +vlog Message # 2362: +There is no additional information for this message. + + +vlog Message # 2363: +There is no additional information for this message. + + +vlog Message # 2364: +There is no additional information for this message. + + +vlog Message # 2365: +There is no additional information for this message. + + +vlog Message # 2366: +There is no additional information for this message. + + +vlog Message # 2367: +There is no additional information for this message. + +This message will be downgraded to a warning with the -permissive argument. +This error message can be suppressed or downgraded to a note or warning. + +vlog Message # 2368: +There is no additional information for this message. + +This message will be downgraded to a warning with the -permissive argument. +This error message can be suppressed or downgraded to a note or warning. + +vlog Message # 2369: +There is no additional information for this message. + + +vlog Message # 2370: +There is no additional information for this message. + + +vlog Message # 2371: +There is no additional information for this message. + + +vlog Message # 2372: +There is no additional information for this message. + + +vlog Message # 2373: +There is no additional information for this message. + + +vlog Message # 2374: +There is no additional information for this message. + + +vlog Message # 2375: +There is no additional information for this message. + + +vlog Message # 2376: +There is no additional information for this message. + + +vlog Message # 2377: +There is no additional information for this message. + + +vlog Message # 2378: +There is no additional information for this message. + + +vlog Message # 2379: +There is no additional information for this message. + + +vlog Message # 2380: +There is no additional information for this message. + + +vlog Message # 2381: +There is no additional information for this message. + + +vlog Message # 2382: +There is no additional information for this message. + + +vlog Message # 2383: +There is no additional information for this message. + + +vlog Message # 2384: +There is no additional information for this message. + + +vlog Message # 2385: +There is no additional information for this message. + + +vlog Message # 2386: +There is no additional information for this message. + + +vlog Message # 2387: +There is no additional information for this message. + + +vlog Message # 2388: +Redeclaration of a port, variable or other identifier within the same scope is illegal. +This message can be suppressed. + +This message will be downgraded to a warning with the -permissive argument. +This error message can be suppressed or downgraded to a note or warning. + +vlog Message # 2389: +There is no additional information for this message. + + +vlog Message # 2390: +There is no additional information for this message. + + +vlog Message # 2391: +There is no additional information for this message. + + +vlog Message # 2392: +There is no additional information for this message. + + +vlog Message # 2393: +There is no additional information for this message. + + +vlog Message # 2394: +There is no additional information for this message. + + +vlog Message # 2395: +There is no additional information for this message. + + +vlog Message # 2396: +There is no additional information for this message. + + +vlog Message # 2397: +There is no additional information for this message. + + +vlog Message # 2398: +There is no additional information for this message. + + +vlog Message # 2399: +There is no additional information for this message. + + +vlog Message # 2400: +A syntax error occurred because an identifier was used where a type +name should have been used. A common mistake that leads to this +situation involves the use of a type name from a SystemVerilog +package. Check for missing package imports. If packages import +other packages with types verify that all needed types are exported. + + +vlog Message # 2401: +A syntax error occurred because SystemVerilog syntax was specified +where Verilog syntax does not allow for a semicolon. For example: + module m; + ; // <-- extra semicolon + endmodule + +This error message can be suppressed or downgraded to a note or warning. + +vlog Message # 2402: +There is no additional information for this message. + + +vlog Message # 2403: +There is no additional information for this message. + + +vlog Message # 2404: +There is no additional information for this message. + + +vlog Message # 2405: +There is no additional information for this message. + + +vlog Message # 2406: +There is no additional information for this message. + + +vlog Message # 2407: +There is no additional information for this message. + + +vlog Message # 2408: +There is no additional information for this message. + + +vlog Message # 2409: +There is no additional information for this message. + + +vlog Message # 2410: +There is no additional information for this message. + + +vlog Message # 2411: +When defining an enum value with the syntax 'name[N:M]' the value for +N and M should be a non negative integral constant indicating the number of enum +values to define.If this error is suppressed then N and M can be a constant +expression with limited references to parameters. Parameters must +be defined in a package and the parameter value must not depend +on any forward references to constant functions. +[DOC: IEEE STD 1800-2012 System Verilog LRM - Table 6-10-Enumeration element ranges]. + +This message will be downgraded to a warning with the -permissive argument. +This error message can be suppressed or downgraded to a note or warning. + +vlog Message # 2412: +When defining an enum value with the syntax 'name[N]' the value for +N should be a positive integral constant indicating the number of enum +values to define.If this error is suppressed then N can be a constant +expression with limited references to parameters. Parameters must +be defined in a package and the parameter value must not depend +on any forward references to constant functions. +[DOC: IEEE STD 1800-2012 System Verilog LRM - Table 6-10-Enumeration element ranges]. + +This message will be downgraded to a warning with the -permissive argument. +This error message can be suppressed or downgraded to a note or warning. + +vlog Message # 2413: +There is no additional information for this message. + + +vlog Message # 2414: +There is no additional information for this message. + + +vlog Message # 2415: +There is no additional information for this message. + + +vlog Message # 2416: +There is no additional information for this message. + + +vlog Message # 2417: +Multiple packed dimensions are not allowed in a verilog module. +[DOC: IEEE Std 1364-1995 Verilog LRM - 4.9 Arrays] + +This message will be an error with the -pedanticerrors argument. + +vlog Message # 2418: +There is no additional information for this message. + + +vlog Message # 2419: +There is no additional information for this message. + + +vlog Message # 2420: +There is no additional information for this message. + + +vlog Message # 2421: +There is no additional information for this message. + + +vlog Message # 2422: +There is no additional information for this message. + + +vlog Message # 2423: +There is no additional information for this message. + + +vlog Message # 2424: +There is no additional information for this message. + + +vlog Message # 2425: +There is no additional information for this message. + + +vlog Message # 2426: +There is no additional information for this message. + + +vlog Message # 2427: +There is no additional information for this message. + + +vlog Message # 2428: +There is no additional information for this message. + + +vlog Message # 2429: +There is no additional information for this message. + + +vlog Message # 2430: +There is no additional information for this message. + + +vlog Message # 2431: +There is no additional information for this message. + + +vlog Message # 2432: +There is no additional information for this message. + + +vlog Message # 2433: +There is no additional information for this message. + + +vlog Message # 2434: +There is no additional information for this message. + + +vlog Message # 2435: +There is no additional information for this message. + + +vlog Message # 2436: +There is no additional information for this message. + + +vlog Message # 2437: +There is no additional information for this message. + + +vlog Message # 2438: +There is no additional information for this message. + + +vlog Message # 2439: +There is no additional information for this message. + + +vlog Message # 2440: +There is no additional information for this message. + + +vlog Message # 2441: +There is no additional information for this message. + + +vlog Message # 2442: +There is no additional information for this message. + + +vlog Message # 2443: +There is no additional information for this message. + + +vlog Message # 2444: +There is no additional information for this message. + + +vlog Message # 2445: +There is no additional information for this message. + + +vlog Message # 2446: +There is no additional information for this message. + + +vlog Message # 2447: +There is no additional information for this message. + + +vlog Message # 2448: +There is no additional information for this message. + + +vlog Message # 2449: +There is no additional information for this message. + + +vlog Message # 2450: +There is no additional information for this message. + + +vlog Message # 2451: +There is no additional information for this message. + + +vlog Message # 2452: +There is no additional information for this message. + + +vlog Message # 2453: +There is no additional information for this message. + + +vlog Message # 2454: +There is no additional information for this message. + + +vlog Message # 2455: +There is no additional information for this message. + + +vlog Message # 2456: +There is no additional information for this message. + + +vlog Message # 2457: +There is no additional information for this message. + + +vlog Message # 2458: +There is no additional information for this message. + + +vlog Message # 2459: +There is no additional information for this message. + + +vlog Message # 2460: +There is no additional information for this message. + + +vlog Message # 2461: +There is no additional information for this message. + + +vlog Message # 2462: +There is no additional information for this message. + + +vlog Message # 2463: +There is no additional information for this message. + + +vlog Message # 2464: +There is no additional information for this message. + + +vlog Message # 2465: +There is no additional information for this message. + + +vlog Message # 2466: +There is no additional information for this message. + + +vlog Message # 2467: +There is no additional information for this message. + + +vlog Message # 2468: +There is no additional information for this message. + + +vlog Message # 2469: +There is no additional information for this message. + + +vlog Message # 2470: +There is no additional information for this message. + + +vlog Message # 2471: +There is no additional information for this message. + + +vlog Message # 2472: +There is no additional information for this message. + + +vlog Message # 2473: +There is no additional information for this message. + + +vlog Message # 2474: +There is no additional information for this message. + + +vlog Message # 2475: +There is no additional information for this message. + + +vlog Message # 2476: +There is no additional information for this message. + + +vlog Message # 2477: +There is no additional information for this message. + + +vlog Message # 2478: +There is no additional information for this message. + + +vlog Message # 2479: +There is no additional information for this message. + + +vlog Message # 2480: +There is no additional information for this message. + + +vlog Message # 2481: +There is no additional information for this message. + + +vlog Message # 2482: +There is no additional information for this message. + + +vlog Message # 2483: +There is no additional information for this message. + + +vlog Message # 2484: +There is no additional information for this message. + + +vlog Message # 2485: +There is no additional information for this message. + + +vlog Message # 2486: +There is no additional information for this message. + + +vlog Message # 2487: +There is no additional information for this message. + + +vlog Message # 2488: +There is no additional information for this message. + + +vlog Message # 2489: +There is no additional information for this message. + + +vlog Message # 2490: +There is no additional information for this message. + + +vlog Message # 2491: +There is no additional information for this message. + + +vlog Message # 2492: +There is no additional information for this message. + + +vlog Message # 2493: +There is no additional information for this message. + + +vlog Message # 2494: +There is no additional information for this message. + + +vlog Message # 2495: +There is no additional information for this message. + + +vlog Message # 2496: +There is no additional information for this message. + + +vlog Message # 2497: +There is no additional information for this message. + + +vlog Message # 2498: +There is no additional information for this message. + + +vlog Message # 2499: +There is no additional information for this message. + + +vlog Message # 2500: +There is no additional information for this message. + + +vlog Message # 2501: +There is no additional information for this message. + + +vlog Message # 2502: +There is no additional information for this message. + + +vlog Message # 2503: +There is no additional information for this message. + + +vlog Message # 2504: +There is no additional information for this message. + + +vlog Message # 2505: +There is no additional information for this message. + + +vlog Message # 2506: +There is no additional information for this message. + + +vlog Message # 2507: +There is no additional information for this message. + + +vlog Message # 2508: +There is no additional information for this message. + + +vlog Message # 2509: +There is no additional information for this message. + + +vlog Message # 2510: +There is no additional information for this message. + + +vlog Message # 2511: +There is no additional information for this message. + + +vlog Message # 2512: +There is no additional information for this message. + + +vlog Message # 2513: +There is no additional information for this message. + + +vlog Message # 2514: +There is no additional information for this message. + + +vlog Message # 2515: +There is no additional information for this message. + + +vlog Message # 2516: +There is no additional information for this message. + + +vlog Message # 2517: +There is no additional information for this message. + + +vlog Message # 2518: +There is no additional information for this message. + + +vlog Message # 2519: +There is no additional information for this message. + + +vlog Message # 2520: +There is no additional information for this message. + + +vlog Message # 2521: +There is no additional information for this message. + + +vlog Message # 2522: +There is no additional information for this message. + + +vlog Message # 2523: +There is no additional information for this message. + + +vlog Message # 2524: +There is no additional information for this message. + + +vlog Message # 2525: +There is no additional information for this message. + + +vlog Message # 2526: +There is no additional information for this message. + + +vlog Message # 2527: +There is no additional information for this message. + + +vlog Message # 2528: +There is no additional information for this message. + + +vlog Message # 2529: +There is no additional information for this message. + + +vlog Message # 2530: +There is no additional information for this message. + + +vlog Message # 2531: +There is no additional information for this message. + + +vlog Message # 2532: +There is no additional information for this message. + + +vlog Message # 2533: +There is no additional information for this message. + + +vlog Message # 2534: +There is no additional information for this message. + + +vlog Message # 2535: +There is no additional information for this message. + + +vlog Message # 2536: +There is no additional information for this message. + + +vlog Message # 2537: +There is no additional information for this message. + + +vlog Message # 2538: +There is no additional information for this message. + + +vlog Message # 2539: +There is no additional information for this message. + + +vlog Message # 2540: +There is no additional information for this message. + + +vlog Message # 2541: +There is no additional information for this message. + + +vlog Message # 2542: +There is no additional information for this message. + + +vlog Message # 2543: +There is no additional information for this message. + + +vlog Message # 2544: +There is no additional information for this message. + + +vlog Message # 2545: +There is no additional information for this message. + + +vlog Message # 2546: +There is no additional information for this message. + + +vlog Message # 2548: +When subclasses override virtual methods, they shall follow the prototype +exactly by having matching return types. +[DOC: IEEE Std 1800-2009 Verilog LRM - Section 8.19 "Virtual Methods"] + +This error message can be suppressed or downgraded to a note or warning. + +vlog Message # 2549: +There is no additional information for this message. + + +vlog Message # 2550: +There is no additional information for this message. + + +vlog Message # 2551: +There is no additional information for this message. + + +vlog Message # 2552: +There is no additional information for this message. + + +vlog Message # 2553: +There is no additional information for this message. + + +vlog Message # 2554: +There is no additional information for this message. + + +vlog Message # 2555: +This warning is only reported with -lint option. + + +vlog Message # 2556: +There is no additional information for this message. + + +vlog Message # 2557: +There is no additional information for this message. + + +vlog Message # 2558: +There is no additional information for this message. + + +vlog Message # 2559: +There is no additional information for this message. + + +vlog Message # 2560: +There is no additional information for this message. + + +vlog Message # 2561: +There is no additional information for this message. + + +vlog Message # 2562: +There is no additional information for this message. + + +vlog Message # 2563: +There is no additional information for this message. + +This message will be an error with the -pedanticerrors argument. + +vlog Message # 2564: +There is no additional information for this message. + +This message will be an error with the -pedanticerrors argument. + +vlog Message # 2565: +There is no additional information for this message. + + +vlog Message # 2566: +There is no additional information for this message. + + +vlog Message # 2567: +There is no additional information for this message. + + +vlog Message # 2568: +There is no additional information for this message. + + +vlog Message # 2569: +There is no additional information for this message. + + +vlog Message # 2570: +A range expression of zero length (e.g. "[5:4]") was found. Most zero-length +ranges are specified in error, as a result of swapping the low-bound and high-bound. +The range will be treated as empty and contains no values--IEEE Standard +1800-2012 section 11.4.13. + + +vlog Message # 2571: +There is no additional information for this message. + + +vlog Message # 2572: +The DPI function/task prototype in the error message is illegal per IEEE 1800-2012. + + +vlog Message # 2573: +There is no additional information for this message. + + +vlog Message # 2574: +There is no additional information for this message. + + +vlog Message # 2575: +There is no additional information for this message. + + +vlog Message # 2576: +If the bitselect address is invalid (it is out of bounds or has one or more x or z bits), +then the value returned by the reference shall be x for 4-state and 0 for 2-state values. +A bit-select or part-select of a scalar, or of a real variable or real parameter, shall be illegal. +[DOC: IEEE Std 1800-2012 Verilog LRM - 11.5.1 Vector bit-select and part-select addressing] + + +vlog Message # 2577: +There is no additional information for this message. + +This message will be an error with the -pedanticerrors argument. + +vlog Message # 2578: +There is no additional information for this message. + + +vlog Message # 2579: +There is no additional information for this message. + + +vlog Message # 2580: +There is no additional information for this message. + + +vlog Message # 2581: +There is no additional information for this message. + + +vlog Message # 2582: +There is no additional information for this message. + + +vlog Message # 2583: +vlog does not check for conflicts with always_comb and always_latch variables +and it is deferred to vopt time. Run vopt for additional design-level checks. + + +vlog Message # 2584: +It is an error if multiple case items match with a unique case expression. +The implementation shall issue a violation report and execute the statement associated +with the matching case_item that appears first in the case statement, +but not the statements associated with other matching case_items. +[DOC: IEEE Std 1800-2012 Verilog LRM - 12.5.3 unique-case, unique0-case, and priority-case] + + +vlog Message # 2585: +A strength value may only be specified in a continuous assignment +in which the left hand side is a net type. +[DOC: IEEE Std 1800-2012 SystemVerilog LRM - Section 10.3] + +This message will be downgraded to a warning with the -permissive argument. +This error message can be suppressed or downgraded to a note or warning. + +vlog Message # 2586: +There is no additional information for this message. + + +vlog Message # 2587: +A task can have time controlling statements but a function cannot. +For functions usage rules, please refer to : +[DOC: IEEE Std 1800-2012 Verilog LRM - 13.4 Functions] + +This message will be downgraded to a warning with the -permissive argument. +This error message can be suppressed or downgraded to a note or warning. + +vlog Message # 2588: +There is no additional information for this message. + + +vlog Message # 2589: +There is no additional information for this message. + + +vlog Message # 2590: +There is no additional information for this message. + + +vlog Message # 2591: +There is no additional information for this message. + + +vlog Message # 2592: +There is no additional information for this message. + + +vlog Message # 2593: +There is no additional information for this message. + + +vlog Message # 2594: +There is no additional information for this message. + + +vlog Message # 2595: +There is no additional information for this message. + + +vlog Message # 2596: +Component name was not found on a downward path while trying to resolve a +hierarchical reference. It may be safe to ignore this message if the +path contains an instance created using the SystemVerilog bind construct. + + +vlog Message # 2597: +There is no additional information for this message. + + +vlog Message # 2598: +There is no additional information for this message. + + +vlog Message # 2599: +There is no additional information for this message. + + +vlog Message # 2600: +There is no additional information for this message. + + +vlog Message # 2601: +There is no additional information for this message. + + +vlog Message # 2602: +There is no additional information for this message. + + +vlog Message # 2603: +The package is being referenced before it has been compiled. A file found +along a -y path is being compiled on-demand. + + +vlog Message # 2604: +There is no additional information for this message. + + +vlog Message # 2605: +The Verilog LRM allows an empty port expressions to define unnamed ports, +in non-ANSI style module headers. A module declared with the port list '()' +is interpreted as having a single unnamed port but most users intend for +that to create a module with no ports. This warning reports any such, +potentially unintended, unnamed ports. + + +vlog Message # 2606: +There is no additional information for this message. + + +vlog Message # 2607: +There is no additional information for this message. + + +vlog Message # 2608: +There is no additional information for this message. + +This message will be an error with the -pedanticerrors argument. + +vlog Message # 2609: +There is no additional information for this message. + + +vlog Message # 2610: +There is no additional information for this message. + + +vlog Message # 2611: +There is no additional information for this message. + + +vlog Message # 2612: +There is no additional information for this message. + + +vlog Message # 2613: +There is no additional information for this message. + + +vlog Message # 2614: +There is no additional information for this message. + + +vlog Message # 2615: +There is no additional information for this message. + + +vlog Message # 2616: +There is no additional information for this message. + + +vlog Message # 2617: +There is no additional information for this message. + + +vlog Message # 2618: +Redeclaration of a port, variable or other identifier within the same scope is illegal. + + +vlog Message # 2619: +There is no additional information for this message. + +This message will be an error with the -pedanticerrors argument. + +vlog Message # 2620: +There is no additional information for this message. + + +vlog Message # 2621: +There is no additional information for this message. + + +vlog Message # 2622: +This error is generated with -pedanticerrors option. + +This message will be an error with the -pedanticerrors argument. + +vlog Message # 2623: +There is no additional information for this message. + + +vlog Message # 2624: +There is no additional information for this message. + + +vlog Message # 2625: +There is no additional information for this message. + + +vlog Message # 2626: +There is no additional information for this message. + + +vlog Message # 2627: +There is no additional information for this message. + + +vlog Message # 2628: +There is no additional information for this message. + + +vlog Message # 2629: +There is no additional information for this message. + + +vlog Message # 2630: +There is no additional information for this message. + + +vlog Message # 2631: +There is no additional information for this message. + + +vlog Message # 2632: +There is no additional information for this message. + + +vlog Message # 2634: +There is no additional information for this message. + + +vlog Message # 2635: +Two or more table entries in a UDP specifying the same output +for the same combination of inputs,including edges, results in a warning. + + +vlog Message # 2636: +There is no additional information for this message. + + +vlog Message # 2637: +There is no additional information for this message. + + +vlog Message # 2638: +A tick (') was found in the source indicating that the complier expects +the name of a compiler directive or a macro name to follow. +The following will produce this warning: `*, ``, or `7. + + +vlog Message # 2639: +Invalid level argument to the directive `line. +Valid values for are 0, 1, and 2. +Usage: + `line "" +Example: + `line 1 "tb.sv" 0 + + +vlog Message # 2640: +There is no additional information for this message. + + +vlog Message # 2641: +There is no additional information for this message. + + +vlog Message # 2642: +There is no additional information for this message. + + +vlog Message # 2643: +A string literal shall be contained in a single line +unless the new line is immediately preceded by a '\' (backslash). +In this case, the backslash and the newline are ignored. +There is no predefined limit to the length of a string literal. +[DOC: IEEE Std 1800-2012 Verilog LRM - 5.9 String literals] + + +vlog Message # 2644: +There is no additional information for this message. + + +vlog Message # 2645: +There is no additional information for this message. + + +vlog Message # 2646: +There is no additional information for this message. + + +vlog Message # 2647: +There is no additional information for this message. + + +vlog Message # 2648: +There is no additional information for this message. + + +vlog Message # 2649: +There is no additional information for this message. + + +vlog Message # 2650: +There is no additional information for this message. + + +vlog Message # 2651: +There is no additional information for this message. + + +vlog Message # 2652: +There is no additional information for this message. + + +vlog Message # 2653: +There is no additional information for this message. + + +vlog Message # 2654: +There is no additional information for this message. + + +vlog Message # 2655: +There is no additional information for this message. + + +vlog Message # 2656: +There is no additional information for this message. + + +vlog Message # 2657: +There is no additional information for this message. + + +vlog Message # 2658: +There is no additional information for this message. + + +vlog Message # 2659: +There is no additional information for this message. + + +vlog Message # 2660: +There is no additional information for this message. + + +vlog Message # 2661: +There is no additional information for this message. + + +vlog Message # 2662: +There is no additional information for this message. + + +vlog Message # 2663: +There is no additional information for this message. + + +vlog Message # 2664: +There is no additional information for this message. + + +vlog Message # 2665: +There is no additional information for this message. + + +vlog Message # 2666: +There is no additional information for this message. + + +vlog Message # 2667: +There is no additional information for this message. + + +vlog Message # 2668: +There is no additional information for this message. + + +vlog Message # 2669: +There is no additional information for this message. + + +vlog Message # 2670: +There is no additional information for this message. + + +vlog Message # 2671: +There is no additional information for this message. + + +vlog Message # 2672: +There is no additional information for this message. + + +vlog Message # 2673: +There is no additional information for this message. + + +vlog Message # 2674: +There is no additional information for this message. + + +vlog Message # 2675: +A module instantiation contains fewer objects in its port list than the +actual module has defined in its port list; therefore, one or more ports +in the module will be unconnected. If all named ports appear to be +accounted for, check for extra commas in the module port list which +cause the definition of null ports. Here is an example of code that +causes this warning to occur: + + module b1(p1,,); + input p1; + initial begin + #10 $displayb("%m",,p1); + end + endmodule + + module top; + reg r1; + b1 u1(r1); + initial r1 = 0; + endmodule + +Note that three port connections are expected because there are two +commas in the module's port list. +This message is controlled by the vsim option +nowarnTFMPC. +[DOC: QuestaSim User's Manual - QuestaSim messages Appendix, + Miscellaneous messages Section] + + +vlog Message # 2676: +There is no additional information for this message. + + +vlog Message # 2677: +There is no additional information for this message. + + +vlog Message # 2678: +There is no additional information for this message. + + +vlog Message # 2679: +There is no additional information for this message. + + +vlog Message # 2680: +There is no additional information for this message. + + +vlog Message # 2681: +There is no additional information for this message. + + +vlog Message # 2682: +There is no additional information for this message. + + +vlog Message # 2683: +There is no additional information for this message. + + +vlog Message # 2684: +A module instantiation contains fewer objects in its port list than the +actual module has defined in its port list; therefore, one or more ports +in the module will be unconnected. If all named ports appear to be +accounted for, check for extra commas in the module port list which +cause the definition of null ports. Here is an example of code that +causes this warning to occur: + + module b1(p1,,); + input p1; + initial begin + #10 $displayb("%m",,p1); + end + endmodule + + module top; + reg r1; + b1 u1(r1); + initial r1 = 0; + endmodule + +Note that three port connections are expected because there are two +commas in the module's port list. +This message is controlled by the vsim option +nowarnTFMPC. +[DOC: QuestaSim User's Manual - QuestaSim messages Appendix, + Miscellaneous messages Section] + + +vlog Message # 2685: +A module instantiation contains fewer objects in its port list than the +actual module has defined in its port list; therefore, one or more ports +in the module will be unconnected. If all named ports appear to be +accounted for, check for extra commas in the module port list which +cause the definition of null ports. Here is an example of code that +causes this warning to occur: + + module b1(p1,,); + input p1; + initial begin + #10 $displayb("%m",,p1); + end + endmodule + + module top; + reg r1; + b1 u1(r1); + initial r1 = 0; + endmodule + +Note that three port connections are expected because there are two +commas in the module's port list. +This message is controlled by the vsim option +nowarnTFMPC. +[DOC: QuestaSim User's Manual - QuestaSim messages Appendix, + Miscellaneous messages Section] + + +vlog Message # 2686: +There is no additional information for this message. + + +vlog Message # 2687: +There is no additional information for this message. + + +vlog Message # 2688: +There is no additional information for this message. + + +vlog Message # 2689: +There is no additional information for this message. + + +vlog Message # 2690: +There is no additional information for this message. + + +vlog Message # 2691: +There is no additional information for this message. + + +vlog Message # 2692: +There is no additional information for this message. + + +vlog Message # 2693: +There is no additional information for this message. + + +vlog Message # 2694: +There is no additional information for this message. + + +vlog Message # 2695: +There is no additional information for this message. + + +vlog Message # 2696: +There is no additional information for this message. + + +vlog Message # 2697: +There is no additional information for this message. + + +vlog Message # 2698: +There is no additional information for this message. + +This error message can be suppressed or downgraded to a note or warning. + +vlog Message # 2699: +There is no additional information for this message. + + +vlog Message # 2700: +There is no additional information for this message. + + +vlog Message # 2701: +There is no additional information for this message. + + +vlog Message # 2702: +There is no additional information for this message. + + +vlog Message # 2703: +There is no additional information for this message. + + +vlog Message # 2704: +The effort required to create the FEC table for the expression is greater +than the limit set by the user (or the tool by default). FEC table can grow +exponentially for complex expressions and can severely impact performance +and memory footprint. This limit is put in place to keep a watch on the +effort involved while creating the FEC table and skip expressions that +exceed the limit. This warning is reported whenever an expression, that +would've otherwise been considered for FEC coverage, was ignored only +because a higher effort was required to create its FEC table, than +the limit set. Please use command-line option '-fecudpeffort' or modelsim.ini +variable 'FecUdpEffort' to increase this limit. Be aware that increasing this +limit may increase compilation, optimization, and simulation time. + + +vlog Message # 2705: +The effort required to create the UDP table for the expression is greater +than the limit set by the user (or the tool by default). UDP table can grow +exponentially for complex expressions and can severely impact performance +and memory footprint. This limit is put in place to keep a watch on the +effort involved while creating the UDP table and skip expressions that +exceed the limit. This warning is reported whenever an expression, that +would've otherwise been considered for UDP coverage, was ignored only +because a higher effort was required to create its UDP table, than +the limit set. Please use command-line option '-fecudpeffort' or modelsim.ini +variable 'FecUdpEffort' to increase this limit. Be aware that increasing this +limit may increase compilation, optimization, and simulation time. + + +vlog Message # 2706: +The effort required to create FEC and UDP tables for the expression is greater +than the limit set by the user (or the tool by default). FEC and UDP tables can grow +exponentially for complex expressions and can severely impact performance +and memory footprint. This limit is put in place to keep a watch on the +effort involved while creating these tables and skip expressions that +exceed the limit. This warning is reported whenever an expression, that +would've otherwise been considered for coverage, was ignored only +because a higher effort was required to create its FEC and UDP tables, than +the limit set. Please use command-line option '-fecudpeffort' or modelsim.ini +variable 'FecUdpEffort' to increase this limit. Be aware that increasing this +limit may increase compilation, optimization, and simulation time. + + +vlog Message # 2707: +There is no additional information for this message. + + +vlog Message # 2708: +There is no additional information for this message. + + +vlog Message # 2709: +There is no additional information for this message. + + +vlog Message # 2710: +There is no additional information for this message. + + +vlog Message # 2711: +There is no additional information for this message. + + +vlog Message # 2712: +There is no additional information for this message. + + +vlog Message # 2713: +There is no additional information for this message. + + +vlog Message # 2714: +There is no additional information for this message. + + +vlog Message # 2715: +There is no additional information for this message. + + +vlog Message # 2716: +There is no additional information for this message. + + +vlog Message # 2717: +There is no additional information for this message. + + +vlog Message # 2718: +The specified port is not connected. See previous error (#2684) for more +information. This message is controlled by the vsim option +nowarnTFMPC. +[DOC: QuestaSim User's Manual - QuestaSim messages Appendix, + Miscellaneous messages Section] + + +vlog Message # 2719: +Parameter types can be declared without an explicit initial type for vlog. +However, a value must be supplied to the parameter during elaboration. + +This error message can be suppressed or downgraded to a note or warning. + +vlog Message # 2720: +Generate begin/end blocks must be within a generate region. Verilog +1364-2005 allowed implicit generate blocks, but SystemVerilog requires +generate blocks to be within explicit generate regions. Generate +regions are formed within generate/endgenerate keyword pairs or as a +part of a loop or conditional generate construct. + +This message will be downgraded to a warning with the -permissive argument. +This error message can be suppressed or downgraded to a note or warning. + +vlog Message # 2721: +coverage fsm_off -fstate is the correct syntax for pragma exclusion +state_variable was not provided if this warning appears. + + +vlog Message # 2722: +coverage fsm_off -ftrans is the correct syntax for pragma exclusion +state_variable was not provided if this warning appears. + + +vlog Message # 2723: +Boolean values are commonly created using enumerated types and the results may not be as expected +when using the inversion operator. It is recommended to resize the enumerated type to one bit or +use the logical negation operator when manipulating boolean enumerated values. + + +vlog Message # 2724: +The IEEE 1800-2009 LRM allows streaming concatenation syntax of the following form: + streaming_concatenation ::= { stream_operator constant_expression stream_concatenation } + + +vlog Message # 2725: +Use of virtual interfaces in assertion or expect is not supported. + + +vlog Message # 2726: +The specified library could not be accessed at the specified location. +Verify that the directories in the path exist and have the proper access +permissions and that the "_info" file (with proper access permissions) +exists. This message might be preceded or followed by another message +that gives more information about the problem. + +The vlib command creates a QuestaSim library. The vmap command creates +the map from a logical library name to the physical library (directory). +Use the vmap command without arguments to find out how all the libraries +are mapped. In the absence of a mapping, the library is searched for in +the current working directory. + +One way this problem can occur is if the mapping for the library in your +modelsim.ini file contains an environment variable that is not set +in your environment. + +This message will be downgraded to a warning with the -permissive argument. +This error message can be suppressed or downgraded to a note or warning. + +vlog Message # 2727: +An implicit coverpoint will be created if cross coverpoint list contains an +identifier. This implicit coverpoint is found to be a duplicate. It can be simply +replaced with the coverpoint explicitly declared. + + +vlog Message # 2728: +The left hand side of the inside operator must be a singular expression. +Also: +When using a range with the inside operator the lower and upper bounds +must be of a singular type for which the relation operators (<=, >=) are +defined. +[DOC: IEEE Std 1800-2009 Verilog LRM - Section 11.4.13 "Set membership operator"] + + +vlog Message # 2729: +Please contact support. + + +vlog Message # 2730: +A variable of the given name could not be found. + + +vlog Message # 2731: +An out-of-block declaration shall be declared in the same scope +as the class declaration and shall follow the class declaration. +[DOC: IEEE Std 1800-2012 Verilog LRM - Section 8.24 "Out-of-Block declaration"] + +This message will be downgraded to a warning with the -permissive argument. +This error message can be suppressed or downgraded to a note or warning. + +vlog Message # 2732: +A parameter of the given name was specified to be overridden +with a type or a value. However, a parameter of the given name +was not found in the target. + +This error message can be suppressed or downgraded to a note or warning. + +vlog Message # 2733: +A parameter of the given name was specified to be overridden +with a type or a value. However, a parameter of the given name +was not found in the target. + +This error message can be suppressed or downgraded to a note or warning. + +vlog Message # 2734: +There is no additional information for this message. + +This error message can be suppressed or downgraded to a note or warning. + +vlog Message # 2735: +Variables of different types, such as a vector and a class handle, +may not be compared. + +This message will be downgraded to a warning with the -permissive argument. +This error message can be suppressed or downgraded to a note or warning. + +vlog Message # 2736: +Section 25.7 of the LRM describes 'import' tasks and functions +in modports, but our support of 'import' with a simple or hierarchical +non-subroutine name (ie, a clocking block) is an extension. + +This message will be an error with the -pedanticerrors argument. + +vlog Message # 2737: +An empty assignment pattern is only legal for a queue, but this +error may be suppressed for a dynamic array. + +This message will be an error with the -pedanticerrors argument. + +vlog Message # 2738: +Only comma-separated lists of attributes are legal. +Questa will accept semicolons rather than a comma. +Note that the -pedanticerrors switch disables this +extension. + +This message will be an error with the -pedanticerrors argument. + +vlog Message # 2739: +The SystemVerilog specification does not allow null +attribute specifications. Note that the -pedanticerrors +switch disables this extension. + +This message will be an error with the -pedanticerrors argument. + +vlog Message # 2740: +Associative or sparse array type are not supported as + DPI tf argument type or a field of tf argument type. + + +vlog Message # 2741: +The rhs is evaluated just once at the time the force is executed +and is applied as though it is constant and does not update the +forced value subsequently when any of the rhs variables change value. + + +vlog Message # 2743: +Non-standard SystemVerilog attributes were found. +The -pedanticerrors switch disables this extension. + +This message will be an error with the -pedanticerrors argument. + +vlog Message # 2744: +It shall be illegal to have an import statement directory within a class scope. +[DOC: IEEE Std 1800-2009 Verilog LRM - Section 26.3 "Referencing data in packages"] + +This message will be downgraded to a warning with the -permissive argument. +This error message can be suppressed or downgraded to a note or warning. + +vlog Message # 2745: +The class resolution operator needs to explicitly use #() syntax +when resolving a parameterized class. For example if the class C is +parameterized then a proper class resolution operator would have the form +'C#()::'. +[DOC: IEEE Std 1800-2017 Verilog LRM - Section 8.25.1 "Class scope resolution operator +for parameterized classes"] + +This message will be downgraded to a warning with the -permissive argument. +This error message can be suppressed or downgraded to a note or warning. + +vlog Message # 2746: +There is no additional information for this message. + + +vlog Message # 2747: +There is no additional information for this message. + + +vlog Message # 2748: +There is no additional information for this message. + + +vlog Message # 2749: +There is no additional information for this message. + + +vlog Message # 2750: +There is no additional information for this message. + + +vlog Message # 2751: +There is no additional information for this message. + + +vlog Message # 2752: +Cells containing continuous assignments to nets and some forces can be optimized under +limited conditions. It is important that any net have only one driver. Forces +must occur inside initial blocks and cannot be released. Forces on nets that +are connected to input ports must use the +nocheckFORPORT setting to optimize as +the forced value will not be propagated to the port's hiconn. + + +vlog Message # 2753: +There is no additional information for this message. + + +vlog Message # 2754: +There is no additional information for this message. + + +vlog Message # 2755: +There is no additional information for this message. + + +vlog Message # 2756: +There is no additional information for this message. + + +vlog Message # 2757: +There is no additional information for this message. + + +vlog Message # 2758: +There is no additional information for this message. + + +vlog Message # 2759: +There is no additional information for this message. + + +vlog Message # 2760: +There is no additional information for this message. + + +vlog Message # 2761: +There is no additional information for this message. + + +vlog Message # 2762: +There is no additional information for this message. + + +vlog Message # 2763: +There is no additional information for this message. + + +vlog Message # 2764: +There is no additional information for this message. + + +vlog Message # 2765: +There is no additional information for this message. + + +vlog Message # 2766: +There is no additional information for this message. + + +vlog Message # 2767: +There is no additional information for this message. + + +vlog Message # 2768: +There is no additional information for this message. + + +vlog Message # 2769: +There is no additional information for this message. + + +vlog Message # 2770: +There is no additional information for this message. + + +vlog Message # 2771: +There is no additional information for this message. + + +vlog Message # 2772: +There is no additional information for this message. + + +vlog Message # 2773: +There is no additional information for this message. + + +vlog Message # 2774: +There is no additional information for this message. + + +vlog Message # 2775: +There is no additional information for this message. + + +vlog Message # 2776: +There is no additional information for this message. + + +vlog Message # 2777: +There is no additional information for this message. + + +vlog Message # 2778: +There is no additional information for this message. + + +vlog Message # 2779: +There is no additional information for this message. + + +vlog Message # 2780: +There is no additional information for this message. + + +vlog Message # 2781: +There is no additional information for this message. + + +vlog Message # 2782: +There is no additional information for this message. + + +vlog Message # 2783: +There is no additional information for this message. + + +vlog Message # 2784: +There is no additional information for this message. + + +vlog Message # 2785: +There is no additional information for this message. + + +vlog Message # 2786: +There is no additional information for this message. + + +vlog Message # 2787: +There is no additional information for this message. + + +vlog Message # 2788: +There is no additional information for this message. + + +vlog Message # 2789: +There is no additional information for this message. + + +vlog Message # 2790: +There is no additional information for this message. + + +vlog Message # 2791: +There is no additional information for this message. + + +vlog Message # 2792: +There is no additional information for this message. + + +vlog Message # 2793: +There is no additional information for this message. + + +vlog Message # 2794: +There is no additional information for this message. + + +vlog Message # 2795: +There is no additional information for this message. + + +vlog Message # 2796: +There is no additional information for this message. + + +vlog Message # 2797: +There is no additional information for this message. + + +vlog Message # 2798: +There is no additional information for this message. + + +vlog Message # 2799: +There is no additional information for this message. + + +vlog Message # 2800: +There is no additional information for this message. + + +vlog Message # 2801: +There is no additional information for this message. + + +vlog Message # 2802: +There is no additional information for this message. + + +vlog Message # 2803: +There is no additional information for this message. + + +vlog Message # 2804: +There is no additional information for this message. + + +vlog Message # 2805: +There is no additional information for this message. + + +vlog Message # 2806: +There is no additional information for this message. + + +vlog Message # 2807: +There is no additional information for this message. + + +vlog Message # 2808: +There is no additional information for this message. + + +vlog Message # 2809: +There is no additional information for this message. + + +vlog Message # 2810: +There is no additional information for this message. + + +vlog Message # 2811: +There is no additional information for this message. + + +vlog Message # 2812: +There is no additional information for this message. + + +vlog Message # 2813: +There is no additional information for this message. + + +vlog Message # 2814: +There is no additional information for this message. + + +vlog Message # 2815: +There is no additional information for this message. + + +vlog Message # 2816: +There is no additional information for this message. + + +vlog Message # 2817: +There is no additional information for this message. + + +vlog Message # 2818: +There is no additional information for this message. + + +vlog Message # 2819: +There is no additional information for this message. + + +vlog Message # 2820: +There is no additional information for this message. + + +vlog Message # 2821: +There is no additional information for this message. + + +vlog Message # 2822: +There is no additional information for this message. + + +vlog Message # 2823: +There is no additional information for this message. + + +vlog Message # 2824: +There is no additional information for this message. + + +vlog Message # 2825: +There is no additional information for this message. + + +vlog Message # 2826: +There is no additional information for this message. + + +vlog Message # 2827: +There is no additional information for this message. + + +vlog Message # 2828: +There is no additional information for this message. + + +vlog Message # 2829: +There is no additional information for this message. + + +vlog Message # 2830: +There is no additional information for this message. + + +vlog Message # 2831: +There is no additional information for this message. + + +vlog Message # 2832: +There is no additional information for this message. + + +vlog Message # 2833: +There is no additional information for this message. + + +vlog Message # 2834: +There is no additional information for this message. + + +vlog Message # 2835: +There is no additional information for this message. + + +vlog Message # 2836: +There is no additional information for this message. + + +vlog Message # 2837: +There is no additional information for this message. + + +vlog Message # 2838: +There is no additional information for this message. + + +vlog Message # 2839: +There is no additional information for this message. + + +vlog Message # 2840: +There is no additional information for this message. + + +vlog Message # 2841: +There is no additional information for this message. + + +vlog Message # 2842: +There is no additional information for this message. + + +vlog Message # 2843: +There is no additional information for this message. + + +vlog Message # 2844: +There is no additional information for this message. + + +vlog Message # 2845: +There is no additional information for this message. + + +vlog Message # 2846: +There is no additional information for this message. + + +vlog Message # 2847: +There is no additional information for this message. + + +vlog Message # 2848: +There is no additional information for this message. + + +vlog Message # 2849: +There is no additional information for this message. + + +vlog Message # 2850: +There is no additional information for this message. + + +vlog Message # 2851: +There is no additional information for this message. + + +vlog Message # 2852: +There is no additional information for this message. + + +vlog Message # 2853: +There is no additional information for this message. + + +vlog Message # 2854: +There is no additional information for this message. + + +vlog Message # 2855: +There is no additional information for this message. + + +vlog Message # 2856: +There is no additional information for this message. + + +vlog Message # 2857: +Questa will optimize cells with up to 64 timing checks. This is an +internal limitation. Questa will work with more timing checks on a +cell than 64, but the cell will not be optimized. + + +vlog Message # 2858: +There is no additional information for this message. + + +vlog Message # 2859: +There is no additional information for this message. + + +vlog Message # 2860: +There is no additional information for this message. + + +vlog Message # 2861: +There is no additional information for this message. + + +vlog Message # 2862: +There is no additional information for this message. + + +vlog Message # 2863: +There is no additional information for this message. + + +vlog Message # 2864: +There is no additional information for this message. + + +vlog Message # 2865: +There is no additional information for this message. + + +vlog Message # 2866: +There is no additional information for this message. + + +vlog Message # 2867: +There is no additional information for this message. + + +vlog Message # 2868: +There is no additional information for this message. + + +vlog Message # 2869: +There is no additional information for this message. + + +vlog Message # 2870: +There may be one or more instances which trigger this warning. + + +vlog Message # 2871: +The specified port is not connected. See previous error (#2684) for more +information. This message is controlled by the vsim option +nowarnTFMPC. +[DOC: QuestaSim User's Manual - QuestaSim messages Appendix, + Miscellaneous messages Section] + + +vlog Message # 2872: +Instantiations for modules containing unnamed ports must connect the ports +by position. An unnamed port is created when a comma succeeds another +comma (",,") in the list of ports in a module declaration or when the +port expression is a bit-select, a part-select, or a concatenation. +[DOC: IEEE Std 1364-1995 Verilog LRM - 12.3 Ports] + +This message will be downgraded to a warning with the -permissive argument. +This error message can be suppressed or downgraded to a note or warning. + +vlog Message # 2873: +A task which has no delay and no DPI task calls is allowed to be in a function. +But a task with delay or DPI task call is not allowed in a function. + + +vlog Message # 2874: +Tasks cannot be called in functions. +Non-blocking task calls are allowed in functions +without -pedanticerrors switch. + +This message will be an error with the -pedanticerrors argument. + +vlog Message # 2875: +Tasks cannot be called in functions as per LRM. +The -pedanticerrors switch disables this extension. + +This message will be an error with the -pedanticerrors argument. + +vlog Message # 2876: +The grammar for SystemVerilog configurations require that +each configuration rule statement and each design statement +be terminated with a semicolon. + +This message will be an error with the -pedanticerrors argument. + +vlog Message # 2877: +The fixed_value pragma must be placed within the declarative region of the module. + + +vlog Message # 2878: +If an interface class extends more than one base interface class +and there are multiple visible definitions for a given name, the +extending class must define the name. + + +vlog Message # 2879: +Tasks cannot be called in final procedure. +Non-blocking task calls are allowed in final procedures +without -pedanticerrors switch. + +This message will be an error with the -pedanticerrors argument. + +vlog Message # 2880: +Tasks cannot be called in final procedures as per LRM. +The -pedanticerrors switch disables this extension. + +This message will be an error with the -pedanticerrors argument. + +vlog Message # 2881: +A task which has no delay and no DPI task call is allowed to be in a final procedure. +But a task with delay or DPI task call is not allowed in a final procedure. + + +vlog Message # 2882: +The qualifier 'virtual' is not legal with an interface class. + +This error message can be suppressed or downgraded to a note or warning. + +vlog Message # 2883: +Interface class parameters, types, and enum constants are only +accessible using a class select (::) reference. + +This error message can be suppressed or downgraded to a note or warning. + +vlog Message # 2884: +There is no additional information for this message. + +This error message can be suppressed or downgraded to a note or warning. + +vlog Message # 2885: +It is illegal for a nested class to extend any class it is contained in: +class outer; + class inner extends outer; //inner may not extend outer + endclass +endclass + + +vlog Message # 2886: +The defaults for interface class method formals are required to be +constant expressions. + +This error message can be suppressed or downgraded to a note or warning. + +vlog Message # 2887: +There is no additional information for this message. + + +vlog Message # 2888: +A static method has no access to nonstatic members (class properties +or methods). +Access to non-static members or to the special 'this' handle within +the body of a static method is illegal. +[DOC: IEEE Std 1800-2009 Verilog LRM - 8.9 Static Methods] + + +vlog Message # 2889: +Unqualified access to non-static members of a class outside of its class scope +is illegal. +Unqualified access to non-static members of a class is limited to +classes which inherit from it. +[DOC: IEEE Std 1800-2009 Verilog LRM - 8.12 Inheritance and Subclasses] + + +vlog Message # 2890: +Please refer to the IEEE 1800-2009 LRM. + + +vlog Message # 2891: +The IEEE 1800-2009 LRM section 13.4, 'Functions', states +that a function shall not contain any time-controlled statements. +Note that fork/join_none blocks may be called from a thread +starting in an initial block or an always block. + + +vlog Message # 2892: +The IEEE 1800-2012 LRM section 23.2.2.3, 'Rules for determining port +kind, data type and direction', requires a net type on non-var and +non-ref ports. The default net type can be changed using the +`default_nettype compiler directive. Alternately the port's net type +can be explicitly set using one of the wire types defined in section +A.2.2.1, 'Net and variable types', under the rule 'net_type'. Also +consider if the port should be a ref port, section 23.2.2.2, or if the +port should be of a variable type. + +The following case illustrates this problem: +`default_nettype none +module top(input logic clk); endmodule + +This can be changed to: +`default_nettype none +module top(input var logic clk); endmodule + +Or: + +`default_nettype wire +module top(input logic clk); endmodule + +/* Which is the same as: */ +module top(input wire logic clk); endmodule + +This error message can be suppressed or downgraded to a note or warning. + +vlog Message # 2893: +The bind mechanism has found an expression type that it does not +support. Please report this error to support. The tool might accept +an equivalent expression written differently. + + +vlog Message # 2894: +In previous versions, nested parameterized classes were not fully +supported and required the "-npcbeta" switch. Full support is now +default and the switch will become unrecognized in a future version. + + +vlog Message # 2895: +The effort required to create FEC and UDP tables for the expression is greater +than the limit set by the user (or the tool by default). FEC and UDP tables can grow +exponentially for complex expressions and can severely impact performance +and memory footprint. This limit is put in place to keep a watch on the +effort involved while creating these tables and skip expressions that +exceed the limit. This warning is reported whenever an expression, that +would've otherwise been considered for coverage, was ignored only +because a higher effort was required to create its FEC and UDP tables, than +the limit set. Please use command-line option '-fecudpeffort' or modelsim.ini +variable 'FecUdpEffort' to increase this limit. Be aware that increasing this +limit may increase compilation, optimization, and simulation time. + + +vlog Message # 2896: +The effort required to create FEC and UDP tables for the expression is greater +than the limit set by the user (or the tool by default). FEC and UDP tables can grow +exponentially for complex expressions and can severely impact performance +and memory footprint. This limit is put in place to keep a watch on the +effort involved while creating these tables and skip expressions that +exceed the limit. This warning is reported whenever an expression, that +would've otherwise been considered for coverage, was ignored only +because a higher effort was required to create its FEC and UDP tables, than +the limit set. Please use command-line option '-fecudpeffort' or modelsim.ini +variable 'FecUdpEffort' to increase this limit. Be aware that increasing this +limit may increase compilation, optimization, and simulation time. + + +vlog Message # 2897: +The standard syntax for the foreach loop variable list is a comma separated list. + +This message will be an error with the -pedanticerrors argument. + +vlog Message # 2898: +"References to automatic variables and elements or members of dynamic +variables shall be limited to procedural blocks." +[DOC: IEEE Std 1800-2011 Verilog LRM - Section 6.21 "Scope and lifetime"] + + +vlog Message # 2899: +The 1800-2009 LRM specifies in section 22.6 that only a 'text_macro_identifier' +may follow an ifdef, an elseif or an ifndef. +[DOC: IEEE Std 1800-2009 Verilog LRM - Section 22.6] + +This message will be an error with the -pedanticerrors argument. + +vlog Message # 2900: +Localparams requires an initialization as it cannot be assigned by +defparam statements or instance parameter value assignments. +Keep in mind that the parameter keyword is a synonym for the localparam +keyword within generate blocks, packages, class bodies, and +compilation-unit scopes. +[DOC: IEEE Std 1800-2012 Section 6.20.4] + + +vlog Message # 2901: +This message is issued when path specified in assertion control task +is not found. This message can be suppressed. + +This error message can be suppressed or downgraded to a note or warning. + +vlog Message # 2902: +A conditional compilation construct was found on the same line as a +macro definition. This can lead to non-portable SV code. The +1800-2009 SV LRM implies in section 22.6 that the conditional +compilation constructs operate on lines of SV code rather than +characters immediately following the `ifdef constructs on the same +line. + +Similarly in section 22.5.1, the body of any `define shall be all arbitrary +text until the end of the line. This warning arises for SV code such as: + + `ifndef A `define B c `endif + +According to a strict 2009 LRM interpretation the `endif should be +considered part of the macro's text body. That is to say that the +`endif does not complete the `ifndef found at the start of the line. +To avoid such amgiguity this should be coded in the following manner: + + `ifndef A + `define B c + `endif + +This message can be suppressed, but when suppressed the behavior of +the composition of these two preprocessor constructs on the same line +is ambiguous. + +This error message can be suppressed or downgraded to a note or warning. + +vlog Message # 2903: +Please refer to the IEEE 1800-2009 LRM section 18.5 "Constraint +blocks." Constraint expression syntax allows for a constraint set to +be a constraint expression. Constraint expressions are not general +SystemVerilog expressions as described in section A.8 of the +grammar. Constraint expressions may contain a distribution. A +distribution may not be immediately enclosed with parenthesis, but it +can be enclosed with curly-braces. For example: + + constraint c1 { + e1 -> {b dist {0:/10, 1:=2};} // OK, curly braces + e2 -> (b dist {0:/10, 1:=2}); // NOT OK, parenthesis not legal + e3 -> (b inside {1'b0, 1'b1}); // OK, parenthesis around 'inside' + } + +This message will be an error with the -pedanticerrors argument. + +vlog Message # 2904: +Currently specify paths to/from ports of type wreal are not supported. + + +vlog Message # 2905: +If formal is of class type then the actual must be assignable to the formal. + + +vlog Message # 2906: +The SystemVerilog preprocessor's line directive requires a parameter +named level. The value of this parameter can be 0, 1 or 2. When this +parameter's value is 2 then the LRM indicates that the preprocessor +has just exited an include file. A mismatch between opening and +closing line directives triggers this error. An example which will +trigger this error: + + `line 66 "test.sv" 0 + `line 3 "include.sv" 1 + `line 67 "bogus.sv" 2 + +In this example, the first directive specifies that the current file +name is "test.sv". The second directive indicates that an include +file has just been entered starting at line 3. The third causes an +error because it states that we are now exiting the include file +named "include.sv" and will continue to read the file where we left +off, which should be named "test.sv". + +The following should read without error: + + `line 66 "test.sv" 0 + `line 3 "include.sv" 1 + `line 67 "test.sv" 2 + + +vlog Message # 2907: +In order to deal with potentially unbounded recursive parameterization, +this implementation limits the depth of parameterization. + + +vlog Message # 2908: +Ref ports of type class handle are not supported in constructors of covergroups. +Such ports are treated as input ports. + + +vlog Message # 2909: +Virtual methods that are overridden must match the prototype +of the superclass exactly. +[DOC: IEEE Std 1800-2009 Verilog LRM - Section 8.19 "Virtual Methods"] + + +vlog Message # 2910: +Virtual methods that are overridden must match the prototype +of the superclass exactly. +[DOC: IEEE Std 1800-2009 Verilog LRM - Section 8.19 "Virtual Methods"] + +This message will be downgraded to a warning with the -permissive argument. +This error message can be suppressed or downgraded to a note or warning. + +vlog Message # 2911: +[DOC: IEEE Std 1800-2009 Verilog LRM - Section 8.19 "Virtual Methods"] + +This message will be downgraded to a warning with the -permissive argument. +This error message can be suppressed or downgraded to a note or warning. + +vlog Message # 2912: +The specified port cannot be connected by name because it does not +exist. + +This error message can be suppressed or downgraded to a note or warning. + +vlog Message # 2913: +It is not advisable to call virtual functions/tasks of the same class +in the class constructor as the object is not created yet. This type of +call may result in unpredictable results. + +This error message can be suppressed or downgraded to a note or warning. + +vlog Message # 2914: +Check the referred expression that may give unpredictable result. + + +vlog Message # 2915: +Check the referred covergroup with or set expressions. + + +vlog Message # 2916: +The compiler is unable to use SystemVerilog 1800 2012 keywords for one +or more reasons. Check to see that the command line does not +explicitly specify an older version of Verilog. Also verify that +source file extensions imply SystemVerilog (i.e.: .sv) if the +SystemVerilog switch (-sv) has not been used. + + +vlog Message # 2917: +The options like +initreg/+noinitreg/+initmem/+noinitmem cannot be applied +to hierarchy within a nested module/program/interface scope. The option is +ignored. +[DOC: QuestaSim Command Reference - vlog/vopt command] + + +vlog Message # 2918: +IEEE Std 1800 does not specify an interface self reference or interface::self() as legal syntax +for referring to the instance itself. +The -pedanticerrors switch disables this extension. + +This message will be an error with the -pedanticerrors argument. + +vlog Message # 2919: +Refer to IEEE Std 1800-2009 BNF. + + +vlog Message # 2920: +Refer to IEEE Std 1800-2009. + + +vlog Message # 2921: +Refer to IEEE Std 1800-2009 18.4 Random Variables for supported data types. + + +vlog Message # 2922: +randc variables are not allowed in this kind of constraints. +[DOC: IEEE Std 1800-2009 Verilog LRM - Section 18.5] + + +vlog Message # 2923: +For more information on constraint blocks, please refer to: +[DOC: IEEE Std 1800-2012 Verilog LRM - 18.5 Constraint blocks] + +This message will be an error with the -pedanticerrors argument. + +vlog Message # 2924: +Refer to IEEE Std 1800-2009 BNF. + + +vlog Message # 2925: +Refer to IEEE Std 1800-2009. + + +vlog Message # 2926: +Refer to IEEE Std 1800-2009. + + +vlog Message # 2927: +Refer to IEEE Std 1800-2009. + + +vlog Message # 2928: +Refer to IEEE Std 1800-2009. + + +vlog Message # 2929: +Refer to IEEE Std 1800-2009. + + +vlog Message # 2930: +Refer to IEEE Std 1800-2009. + + +vlog Message # 2931: +Refer to IEEE Std 1800-2009. + +This message will be an error with the -pedanticerrors argument. + +vlog Message # 2932: +Refer to IEEE Std 1800-2009. + +This message will be an error with the -pedanticerrors argument. + +vlog Message # 2933: +Refer to IEEE Std 1800-2009. + + +vlog Message # 2934: +Refer to IEEE Std 1800-2009. + + +vlog Message # 2935: +Refer to IEEE Std 1800-2009 BNF. + + +vlog Message # 2936: +Refer to IEEE Std 1800-2009 BNF. + + +vlog Message # 2937: +[DOC: IEEE Std 1800-2009 Verilog LRM - Section 18.5.11 "Functions in Constraints"] + + +vlog Message # 2938: +Refer to IEEE Std 1800-2009 BNF. + + +vlog Message # 2939: +Refer to IEEE Std 1800-2009 BNF. + + +vlog Message # 2940: +Refer to IEEE Std 1800-2009 BNF. + + +vlog Message # 2941: +A compiler error shall be issued if the specified variable does not exist +within the class hierarchy or it exists but is not declared as rand or +randc. +[DOC: IEEE Std 1800-2009 Verilog LRM - Section 18.8] + + +vlog Message # 2942: +The constraint_mode() method is built-in and cannot be overridden. +[DOC: IEEE Std 1800-2009 Verilog LRM - Section 18.9] + + +vlog Message # 2943: +The prototypes for these built-in functions are: +function void pre_randomize(); +function void post_randomize(); +[DOC: IEEE Std 1800-2009 Verilog LRM - Section 18.6.2] + + +vlog Message # 2944: +LRM allows function calls in the constraint expressions, but there are +some restrictions on these function calls. Refer to LRM for details +[DOC: IEEE Std 1800-2009 Verilog LRM - Section 18.5.11 Functions in Constraints + + +vlog Message # 2945: +This error is generated with -pedanticerrors option. + +This message will be an error with the -pedanticerrors argument. + +vlog Message # 2946: +Refer to IEE Std 1800-2009 Verilog LRM. + + +vlog Message # 2947: +Refer to IEE Std 1800-2009 Verilog LRM. + + +vlog Message # 2948: +Refer to IEE Std 1800-2009 Verilog LRM. + + +vlog Message # 2949: +Refer to IEE Std 1800-2009 Verilog LRM. + + +vlog Message # 2950: +Refer to IEE Std 1800-2009 Verilog LRM. + + +vlog Message # 2951: +Use '==' in constraint expression instead of '='. + + +vlog Message # 2952: +No 'randc' variables shall appear in uniqueness constraints. +[DOC: IEEE Std 1800-2012 Verilog LRM - Section 18.5.5 Uniqueness Constraints] + + +vlog Message # 2953: +The 'static' qualifier may only be used when declaring a task or a +function within a class body. An out-of-block task or function +declaration may have a prototype within the class body that contains +the 'static' qualifier. A task or function with a 'static' prototype +will be static even though the out-of-block definition does not use +the 'static' keyword. Please see IEEE 1800-2012 section 8.24. An +example exists in section 8.25.1. This message may be promoted to an +error. If this message is not an error then the 'static' qualifier +will be ignored. + +This message will be an error with the -pedanticerrors argument. + +vlog Message # 2954: +Only a scalar variable of integral type or an unpacked array variable whose +leaf element type is integral, or a slice of such a variable can be specified +for uniqueness constraint. +[DOC: IEEE Std 1800-2012 Verilog LRM - Section 18.5.5 Uniqueness Constraints] + + +vlog Message # 2955: +There is no additional information for this message. + + +vlog Message # 2956: +A constraint_set of the form '{expression};' is different from one of the form '{expression;}'. +Putting a ';' after the '{}' causes a different interpretation. '{expression};' represents +a concatenation expression. For example, in 'if (a) {};', the '{}' is an empty queue which is +type converted to the boolean value FALSE. In 'if (a) {}', the '{}' is an empty constraint_set +and is equivalent to the boolean value TRUE. + + +vlog Message # 2957: +This is a suppressible error for writing outside the bounds of a net array. +Note that reading from the out-of-bounds elements may result in +unpredictable values. + +This error message can be suppressed or downgraded to a note or warning. + +vlog Message # 2958: +There is no additional information for this message. + + +vlog Message # 2959: +Free variables are not assigned values based on assumptions. +They are assigned values based on assignments only. + + +vlog Message # 2960: +A streaming_concatenation shall be used either as the target of an assignment, +or as the source of an assignment, or as the operand of a bit-stream cast, +or as a stream_expression in another streaming_concatenation. +[DOC: IEEE Std 1800-2012 Verilog LRM - 11.4.14 Streaming operators (pack/unpack)] + +This message will be an error with the -pedanticerrors argument. + +vlog Message # 2961: +Refer to IEEE Std 1800-2009. + + +vlog Message # 2962: +A macro name follows the naming rules for normal SystemVerilog identifiers. +Some non-compliant names or numbers are allowed by this implementation. +Note that the -pedanticerrors switch disables this +extension. + + +vlog Message # 2963: +A macro name follows the naming rules for normal SystemVerilog identifiers. +Some non-compliant names or numbers are allowed by this implementation. +Note that the -pedanticerrors switch disables this +extension. + + +vlog Message # 2964: +Only variable and literal expressions are supported as instance parameters when +the bind statement is elaborated in vsim instead of vopt. This can happen when +either the bind statement is being compiled with -novopt option, or the design-unit +containing bind statement is being loaded together with an optimized top in vsim. +In case of former, please use vopt flow. In case of later, please run vopt on the +design-unit containing the bind statement. + + +vlog Message # 2965: +Only variable and numeric literal expressions are supported as actual parameters when +the bind statement is elaborated in vsim instead of vopt. This can happen when +either the bind statement is being compiled with -novopt option, or the design-unit +containing bind statement is being loaded together with an optimized top in vsim. +In case of former, please use vopt flow. In case of later, please run vopt on the +design-unit containing the bind statement. + + +vlog Message # 2966: +Only literal expressions are supported as indices in a bind target hierarchical reference when +the bind statement is elaborated in vsim instead of vopt. This can happen when +either the bind statement is being compiled with -novopt option, or the design-unit +containing bind statement is being loaded together with an optimized top in vsim. +In case of former, please use vopt flow. In case of later, please run vopt on the +design-unit containing the bind statement. + + +vlog Message # 2967: +There is no additional information for this message. + + +vlog Message # 2968: +This error message may be suppressed. When this happens the uwire net +type is considered to be a standard wire net type. + +This error message can be suppressed or downgraded to a note or warning. + +vlog Message # 2969: +Tasks with delay cannot be called in action block. +of final deferred assertions. The action block of final +deferred assertion executes in postponed region. As per LRM, +tasks that have delay cannot be executed in postponed region. + + +vlog Message # 2970: +Array lengths must match. + + +vlog Message # 2971: +Assigning one array to another requires that the element type of the +right hand side array be assignment compatible with the left hand side +array. + +This error message can be suppressed or downgraded to a note or warning. + +vlog Message # 2972: +Assigning one array to another requires that the element type of the +right hand side array be assignment compatible with the left hand side +array. For strict LRM compliance, derived classes are not equivalent +with their base classes. + +This message will be an error with the -pedanticerrors argument. + +vlog Message # 2973: +A matching type by the same name was imported into this scope. +Please consider using a different identifier, or remove the +extraneous type definition. + +The actual type definition of a forward typedef declaration shall be +resolved within the same local scope or generate block +[DOC: IEEE Std 1800-2012 Verilog LRM - Section 6.18 User-defined types] + +This message will be an error with the -pedanticerrors argument. + +vlog Message # 2974: +This message will be issued when there is some internal problem. + + +vlog Message # 2975: +$inferred_clock and $inferred_disable cannot be used anywhere. +except as default arguments in the decalaration of properties, +sequences and checkers. + + +vlog Message # 2976: +If $inferred_clock is used as default argument for a sequence with +a method call (triggered or matched), it is not supported. It will be +supported some time in future. + + +vlog Message # 2977: +If $inferred_clock is used as default argument for a sequence, property +or a checker and corresponding argument is not supplied, then a clock should +be inferrable at the instantion point of sequence, property or the checker. +If no clock can be inferred, the error is issued and the user should provide an +explicit clock event expression at the instantiation point. + +This error message can be suppressed or downgraded to a note or warning. + +vlog Message # 2978: +If $inferred_clock is used as default argument for a sequence, property +or a checker, the formal corresponding to that must have either event type +or no type. + + +vlog Message # 2979: +This message is issued when either the psl file syntax does not match with +the compiler version or the type of compiler invoked for the psl file is +incorrect. Please check the command line options to make sure correct type +(Verilog or VHDL) is specified while specifying the psl file. + + +vlog Message # 2980: +The IEEE 1800-2012 LRM allows streaming concatenation syntax of the following form: + streaming_concatenation ::= { stream_operator [ slice_size ] stream_concatenation } + + +vlog Message # 2981: +The optimiser has created a new specialisation of the class. + + +vlog Message # 2982: +The optimiser was not able to construct a fast specialisation for this +set of class parameter bindings. + + +vlog Message # 2983: +When running with -xclassStrict every specialisation of a parameterised class must +map to an optimised class specialisation. Not such specialisation was located for +this instance. + + +vlog Message # 2984: +There is no additional information for this message. + + +vlog Message # 2985: +There is no additional information for this message. + + +vlog Message # 2986: +A hierarchical reference is not a legal constant primary. As a result, +no constant expression may use a hierarchical reference. Constant +expressions are required in contexts such as generate loop contexts, parameter +overrides, part select widths, and wire and variable sizes. + +This error message can be suppressed or downgraded to a note or warning. + +vlog Message # 2987: +There is no additional information for this message. + +This error message can be suppressed or downgraded to a note or warning. + +vlog Message # 2988: +IEEE 1800-2005 replaced the Accellera "$typeof" system function with the +"type" operator. For compatibility with the IEEE standards, all +uses of $typeof should be replaced. + + +vlog Message # 2989: +If a formal has $inferred_clock as default argument, and no actual argument is specified +then that formal can be used only in the clock expressions. + + +vlog Message # 2990: +Does the operator require that the operand be of a packed type? + + +vlog Message # 2991: +There is no additional information for this message. + + +vlog Message # 2992: +There is no additional information for this message. + +This message will be an error with the -pedanticerrors argument. + +vlog Message # 2993: +There is no additional information for this message. + +This message will be an error with the -pedanticerrors argument. + +vlog Message # 2994: +There is no additional information for this message. + +This message will be an error with the -pedanticerrors argument. + +vlog Message # 2995: +There is no additional information for this message. + +This message will be an error with the -pedanticerrors argument. + +vlog Message # 2996: +There is no additional information for this message. + +This message will be an error with the -pedanticerrors argument. + +vlog Message # 2997: +There is no additional information for this message. + +This message will be an error with the -pedanticerrors argument. +This error message can be suppressed or downgraded to a note or warning. + +vlog Message # 2998: +There is no additional information for this message. + +This message will be an error with the -pedanticerrors argument. + +vlog Message # 2999: +Width of enum literal must match with the enum's declaration width. + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3000: +The -t option specifies the simulation time resolution. +The format is: -t [] +The multiplier can be 1, 10, or 100. +The time_unit must be one of the following: fs, ps, ns, us, ms, sec. +There must be no space between the multiplier and the time_unit. +[DOC: QuestaSim Command Reference - vsim command] + + +vsim Message # 3001: +Each PLI/VPI shared library must contain one of the following entry points: + a veriusertfs table + an init_usertfs function + a vlog_startup_routines table +[DOC: QuestaSim User's Manual - Verilog Simulation Chapter] + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3002: +The loading of a shared library can fail for a variety of reasons. +There should be an additional message from the loader indicating the +problem. Verify that the full path to the shared library is correct +and that the shared library is marked as readable. On Solaris, you +might need to set the LD_LIBRARY_PATH environment variable. Also, if +the specification of the shared library contains a reference to an +environment variable, make sure the environment variable has a value. +[DOC: QuestaSim User's Manual - Verilog Simulation Chapter] + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3003: +The specified system task or function was not registered with the +simulator through a call to init_usertfs() or through a veriusertfs +or vlog_startup_routines table. Verify that the shared library +containing the definition and registration of the system task/function +is being correctly loaded into the simulator. This message is controlled +by the vsim option +nowarnTOFD. +[DOC: QuestaSim User's Manual - Verilog Simulation Chapter] + + +vsim Message # 3004: +While performing the negative timing constraint algorithm on each module +that contains timing checks with delayed net arguments, a timing check +with a negative adjusted setup or hold limit was encountered. The +negative timing constraint algorithm attempts to find a set of delays +for the timing check delayed net arguments such that all negative limits +can be converted to non-negative limits with respect to the delayed nets. +If there is no solution for a set of limits, then the algorithm sets one +of the negative limits to zero and recalculates the delays. This process +is repeated until a solution is found. A warning message is issued for +each negative limit that is set to zero. This warning is controlled by +the vsim option +ntc_warn. +[DOC: QuestaSim User's Manual - Verilog Simulation Chapter] + + +vsim Message # 3005: +An unrecoverable error was encountered while QuestaSim was loading or +closing a design, restarting, or shutting down. + + +vsim Message # 3006: +Too many parameters were specified for a module instance. +Here is an example of code that will cause this warning to occur: + + module top; + b #(1,2) u1(y, a, b, c); + endmodule + + module b(y, a, b, c); + output y; + input a, b, c; + parameter p = 0; + c u1(); + initial $display("b=%d",p); + endmodule + + module c; + parameter p = 0; + initial $display("c=%d",p); + endmodule + +Note that module b contains only one parameter. The extra parameter in +the module instantiation statement is illegal. + +You can also get this message if you attempt to override a localparameter +(which is illegal) with an ordered parameter list. For example: + +module a; + parameter a = 1; + localparam c = 3; + parameter b = 2; +endmodule + +module top; + a #(4, 5, 6) u1(); +endmodule + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3007: +Too many levels of defparams were detected. The limit is specified in +the message. Check parameter assignments for a circular dependency. +Here is a simple example of something that causes this warning: + + parameter a = 5; + parameter b = a + 1; + defparam a = b; + +The defparam causes a to change, which then causes b to change. When b +changes, the defparam re-executes and causes a to change, which causes +b to change. This continues until the limit is reached. + +Since this is only a warning, elaboration continues. Each parameter +involved in the iteration will contain the last value set on it +before the simulator gave up because the iteration limit was exceeded. +Your design may not simulate as expected. Find the circular dependency, +if one exists, or look for a place where more than the specified limit +of defparams occurs and change your code so that there is no circular +dependency and the depth of defparams fits within the limit. + + +vsim Message # 3008: +While looking up an object by name, an upward reference through a higher +level of hierarchy was found instead of the expected downward reference +through an instance at the current level of hierarchy. Here is an example +of code that causes this warning to occur: + + module lower; + endmodule + + module mid; + reg x; + lower u2 (); + initial begin + x = 0; + #20 x = 1; + #20 x = 0; + #20 $finish; + end + endmodule + + module top; + wire x; + mid u1 (); + assign x = u1.u2.u1.x; + initial $monitor( $stime,, x,, u1.x); + endmodule + +While trying to resolve the reference to u1.u2.u1.x, the compiler determines +that the second u1 resolves to the module 'mid', which is an unexpected +upward reference. +This warning is controlled by the vsim option +nowarnCNNODP. + + +vsim Message # 3009: +A module without a `timescale directive in effect, and without +explicit timeunit and timeprecision declarations, uses the +simulator resolution limit for both its time unit and time +precision. This may result in incorrect delays and unintentional +behavior in the module. Beware of simulator performance impact, +and consider using the vlog -timescale or vopt -timescale options +as a workaround. This message can be downgraded to a warning with +-warning 3009, suppressed with -suppress 3009, or suppressed +with +nowarnTSCALE. +[DOC: QuestaSim User's Manual - Verilog Simulation Chapter] + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3010: +A module without a `timescale directive in effect, and without +explicit timeunit and timeprecision declarations, uses the +simulator resolution limit for both its time unit and time +precision. This may result in incorrect delays and unintentional +behavior in the module. Beware of simulator performance impact, +and consider using the vlog -timescale or vopt -timescale options +as a workaround. This message can be downgraded to a warning with +-warning 3010, suppressed with -suppress 3010, or suppressed +with +nowarnTSCALE. +[DOC: QuestaSim User's Manual - Verilog Simulation Chapter] + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3011: +The Verilog bidirectional pass switch primitives (tran, tranif0, +tranif1, rtran, rtranif0, and rtranif1) are not guaranteed to function +properly if a VHDL signal is connected to a Verilog port that is also +connected to a bidirectional pass switch. In this case, the pass switch +works only if it is driven in only one direction and only if the signal +originates in VHDL. The specification of how VHDL signals and ports are +resolved precludes simulation of bidirectional pass switches. +(They cannot be modeled in VHDL.) + + +vsim Message # 3012: +A defparam statement cannot be used to define the value of a specparam. + + +vsim Message # 3013: +Local parameters cannot be modified with a defparam statement or by an +ordered or named parameter value assignment. Local parameters can be +assigned to a constant expression containing a parameter, which itself +can be modified with the defparam statement or by an ordered or named +parameter value assignment. Parameters defined within a package, $unit, +or generate construct are treated as local parameters. + + +vsim Message # 3014: +Verilog module ports can be declared such that two or more ports share +the same internal net, having the effect of shorting the externally +connected nets. A VHDL signal connected to a Verilog "shorted" port +is not guaranteed to function properly. The specification of how VHDL +signals and ports are resolved precludes simulation of shorted ports. +(They cannot be modeled in VHDL.) + + +vsim Message # 3015: +The size in bits of an object connected to a port must match the size +in bits of the port. Here is an example of code that causes this warning to occur: + + module bottom(i1, o1); + input i1; + output o1; + wire [0:4] i1; + wire [0:4] o1; + assign o1 = i1; + endmodule + + module top; + reg [4:0] r1; + wire [1:0] w1; + bottom b1 (r1,w1); + initial begin + $monitor("w1 = %b", w1); + #10 r1 = 'b00000; + #10 r1 = 'b00011; + #10 r1 = 'b00001; + end + endmodule + +Note that port 'o1' is 5 bits wide whereas wire 'w1' is only 2 bits wide. +This message is controlled by the vsim option +nowarnPCDPC. + + +vsim Message # 3016: +The type of the specified object in a module instantiation port list is +incompatible with the type of the port to which it is being connected. +This can happen when ports are collapsed and, for example, a tri0 net +ends up collapsed onto a tri1 net. + + +vsim Message # 3017: +A module instantiation contains fewer objects in its port list than the +actual module has defined in its port list; therefore, one or more ports +in the module will be unconnected. If all named ports appear to be +accounted for, check for extra commas in the module port list that +cause the definition of null ports. Here is an example of code that +causes this warning to occur: + + module b1(p1,,); + input p1; + initial begin + #10 $displayb("%m",,p1); + end + endmodule + + module top; + reg r1; + b1 u1(r1); + initial r1 = 0; + endmodule + +Note that three port connections are expected because there are two +commas in the module's port list. +This message is controlled by the vsim option +nowarnTFMPC. +[DOC: QuestaSim User's Manual - QuestaSim messages Appendix, + Miscellaneous messages Section] + + +vsim Message # 3018: +The object connected to a UDP terminal at the specified connection point +in the terminal list of an array of UDP instances must be either one bit +wide (so that the terminal in each UDP instance is connected to the same +bit) or of a width equal to the number of UDP instances (so that the +terminal in each instance is connected to a different bit). + + +vsim Message # 3019: +Too many delay parameters were provided to a UDP instance. + + +vsim Message # 3020: +When the second argument to $deposit is wider than the first argument +the upper bits of the value of the second are ignored. + + +vsim Message # 3021: +$printtimescale can be specified with or without an argument. When no +argument is specified, $printtimescale displays the time unit and +precision of the module that is the current scope. When an argument is +specified, the argument must be a hierarchical identifier of a module +and $printtimescale displays the time unit and precision of that module. + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3022: +The units_number (1st) argument to $timeformat must be an integer in the +range 0 to -15 inclusive. This argument represents a time unit. For +example, -9 represents '1 ns'. + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3023: +The precision_number (2nd) argument to $timeformat must be an integer in +the range 0 to 15 inclusive. This argument controls the number of digits +of a time value printed after the decimal point. + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3024: +The suffix_string (3rd) argument to $timeformat must be non-NULL. It can +be an empty string. It is normally used to specify the type of time units; +for example, " ns". + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3025: +The field_width (4th) argument to $timeformat must be an integer in the +range 0 to 40 inclusive. This value controls the minimum field width for +all %t formats. + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3026: +No files have been opened with $dumpports(), therefore there are no +files to which the limit can be applied. + + +vsim Message # 3027: +The $sdf_annotate configuration file argument is not supported in +QuestaSim. This argument is ignored and can be left null in order to +use succeeding arguments. + + +vsim Message # 3028: +The $sdf_annotate log file argument is not supported in QuestaSim. +This argument is ignored and can be left null in order to use +succeeding arguments. + + +vsim Message # 3029: +While creating an instance of a system function, it was found that a +system task of that name was registered either through the PLI or as +a built-in systf. This is an error because the HDL code will expect +the system function to return a value, but the actual system task +that was registered will not do so. If you wish to use the system +task here, you should remove the return value. + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3030: +A NULL value was passed as the specified argument to the specified PLI +function that requires a non-NULL value for this argument. +[DOC: IEEE Std 1364-1995 Verilog LRM - PLI Sections 17-21] + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3031: +An invalid value was passed as the specified argument to the specified +PLI function. +[DOC: IEEE Std 1364-1995 Verilog LRM - PLI Sections 17-21] + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3032: +While creating a setuphold or recrem timing check, a width difference +was detected between the reference event and the delayed reference or +the data event and the delayed data. + + +vsim Message # 3033: +The specified design unit could not be found for instantiation. If the +specified design unit does not contain a library indication then this +message should be followed by a list of libraries that were searched +when trying to locate a matching design unit. + + +vsim Message # 3034: +The compiled version of the specified design unit does not match what +was originally compiled with -fast for this instantiation. + + +vsim Message # 3035: +This warning occurs when the level of an instantiation reaches a certain +depth. It indicates that the instantiation might be recursive. A further +attempt is made to complete the instantiation. If the maximum depth +is reached then an elaboration error is generated. + + +vsim Message # 3036: +Instantiation of the specified design unit reached the maximum +allowable level; therefore, the instantiation has been aborted. +Check the specified area of the design for recursive instantiation. + + +vsim Message # 3037: +An instance name was not supplied in an instantiation of the specified module. + + +vsim Message # 3038: +The specified index of the range of the specified array of instances was +modified after the instantiation of the array of instances. This can +occur if the instantiated module uses a defparam to modify a parameter +that is used in indexing an array of instances of that module. + + +vsim Message # 3039: +Instantiation of the specified design unit failed either due to +licensing or due to not being able to load package Standard (VHDL). + + +vsim Message # 3040: +A -g/-G generic/parameter specified on the vsim command line was not +found in the design being simulated; or a generic/parameter set via +the foreign interface was not found in the region being loaded; +or a parameter in an instantiation of a VHDL design unit doesn't exist. +Verify that the generic/parameter name is spelled correctly and that +the generic/parameter exists at the expected location in the design. +It may be necessary to add -floatparameters to the vopt command line to +preserve visibility of the generic/parameter from vsim. + + +vsim Message # 3041: +A non-numeric index was detected in a reference to the specified +instance array. + + +vsim Message # 3042: +An index outside of the range of the specified instance array was +detected in a reference to the instance array. + + +vsim Message # 3043: +The specified name in a simple or hierarchical reference cannot be found +as an instance or object in the design. +If the reference is a VHDL external name or is otherwise a hierarchical +reference into a VHDL scope, a common possible reason the name cannot be +found is that the name denotes a PROCESS statement label or a subprogram +name; such external names are illegal in the VHDL language (see message +#8868 as well). Another possible reason the name cannot be found is +that a pathname element denotes an instance that has not yet been +elaborated. In particular, an alias that denotes an external name +cannot be declared in the declarative region in which an instance being +referenced occurs. + + +vsim Message # 3044: +The specified object name was used in a place where the type of that +object is not allowed. For example, using the hierarchical name of a +1-bit register as an index into a multi-bit net would produce this message. + + +vsim Message # 3045: +Not enough arguments are being passed to the specified task or function. + + +vsim Message # 3046: +Too many arguments are being passed to the specified task or function. + + +vsim Message # 3047: +An output or inout argument of a task must be an expression that is +valid on the left-hand side of a procedural assignment. + + +vsim Message # 3048: +The starting bound of an indexed part-select is out of range of the +declared bounds of the specified object. + + +vsim Message # 3049: +The ending bound of an indexed part-select is out of range of the +declared bounds of the specified object. + + +vsim Message # 3050: +The value being supplied to the specified parameter from a -g/-G +specification is invalid for that parameter. + + +vsim Message # 3051: +This message can be produced because of the association of a VHDL +array-type generic (whose elements are not an enumerated type) with a +Verilog real-type parameter, which is not allowed. It can also be +produced if a VHDL generic of an unsupported type (such as record, +access, or file) is associated with a Verilog parameter. + + +vsim Message # 3052: +A VHDL array-type generic contains more bits than the Verilog parameter +to which it is being associated. + + +vsim Message # 3053: +An out or inout port is connected to something that is not a net. This +error can occur if a constant, register, literal, or some other expression that +cannot be driven is connected to an out or inout port. +[DOC: IEEE Std 1364-1995 Verilog LRM - 12.3.6 Connecting dissimilar ports, +12.3.7 Port connection rules] + +In system verilog,this error can occur if an inout port is connected to something that is +not a net, like if a register ,literal or some other expression that cannot be driven is +connected to inout port. It can also arise if an illegal lvalue (constant) is connected to +an out or inout port + +If suppressed, the port (out / inout) will not be connected. + +This message will be downgraded to a warning with the -permissive argument. +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3054: +The object connected to a port at the specified connection point in the +port list of an array of instances must be either one bit wide (so that +the port in each instance is connected to the same bit) or of a width +equal to the number of instances (so that the port in each instance is +connected to a different bit). + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3055: +The connected VHDL signal is not one of the supported types for +connecting to a Verilog port. The supported types are bit, bit_vector, +std_ulogic, std_logic, std_ulogic_vector, std_logic_vector, vl_ulogic, +vl_logic, vl_ulogic_vector, and vl_logic_vector. +[DOC: QuestaSim User's Manual - Mixed VHDL and Verilog Designs Chapter] + + +vsim Message # 3056: +When instantiated from VHDL, a Verilog port must be connected to a VHDL +signal or left open. It cannot be connected to a VHDL value. + + +vsim Message # 3057: +A VHDL scalar signal can be connected to a Verilog port only if the +Verilog port is a scalar. A VHDL array signal can be connected to a +Verilog port only if the Verilog port is a vector. +[DOC: QuestaSim User's Manual - Mixed VHDL and Verilog Designs Chapter] + + +vsim Message # 3058: +When a Verilog vector port is connected to a VHDL array, the array +length of the VHDL array and the width of the Verilog port must be the +same. +[DOC: QuestaSim User's Manual - Mixed VHDL and Verilog Designs Chapter] + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3059: +A VHDL scalar signal can be connected to a Verilog port only if the +Verilog port is a scalar. A VHDL array signal can be connected to a +Verilog port only if the Verilog port is a vector. +[DOC: QuestaSim User's Manual - Mixed VHDL and Verilog Designs Chapter] + + +vsim Message # 3060: +In a mixed language instantiation, the specified Verilog port could +not be found in the associated VHDL entity. Verify that the correct +VHDL/Verilog connection is being made and that extended identifiers +are being used if necessary. +[DOC: QuestaSim User's Manual - Mixed VHDL and Verilog Designs Chapter] + + +vsim Message # 3061: +Too many Verilog ports were specified in a mixed VHDL/Verilog +instantiation. Verify that the correct VHDL/Verilog connection is +being made and that the number of ports matches. +[DOC: QuestaSim User's Manual - Mixed VHDL and Verilog Designs Chapter] + + +vsim Message # 3062: +All ports in a Verilog module that is being instantiated from VHDL must +be named. (An unnamed port is created when one comma in a port list +follows another comma with no intervening text.) +[DOC: QuestaSim User's Manual - Mixed VHDL and Verilog Designs Chapter] + + +vsim Message # 3063: +The specified VHDL port cannot be found by that name in the Verilog +module to which it is being connected. Verify that the correct +VHDL/Verilog connection is being made and that extended identifiers +are being used if necessary. +[DOC: QuestaSim User's Manual - Mixed VHDL and Verilog Designs Chapter] + + +vsim Message # 3064: +This message is notification that the internal string buffer has +wrapped to the beginning. +[DOC: IEEE Std 1364-1995 Verilog LRM - 18.9 String handling] + + +vsim Message # 3065: +The output of a UDP is connected to something other than a net. An +object connected to the output of a UDP must be something that can be +driven, therefore an object like a register or a constant is illegal. +[DOC: IEEE Std 1364-1995 Verilog LRM - 12.3.7 Port connection rules] + + +vsim Message # 3066: +The number of bits in the actual port(s) at the specified port +connection does not equal the number of bits for the associated port +of the instance or instance array. + + +vsim Message # 3067: +All modules instantiated within or below a non-debug module must be +compiled with the -nodebug option. +[DOC: QuestaSim User's Manual - Source code security and -nodebug Section] + + +vsim Message # 3068: +An invalid argument is being passed to the specified system task or function. + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3069: +The specified argument to the specified system task or function is invalid. + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3070: +Too many arguments are being passed to the specified system task or function. + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3071: +Not enough arguments are being passed to the specified system task or function. + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3072: +Arguments are being passed to the specified system task or function +that takes no arguments. + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3073: +The wrong number of arguments are being passed to the specified system +task or function. + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3074: +The first argument to $deposit must be a net or a register. + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3075: +The second argument to $deposit must be a literal value or a register. + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3076: +If the width of the value of the second argument to $deposit is narrower +than the width of the first argument (or one is of type real and the +other is not) then this $deposit call is ignored. + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3077: +The specified function takes only one argument that is an object of type +real. + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3078: +$getpattern can be used only in a continuous assignment statement where +the left-hand side is a concatenation of scalar nets. + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3079: +The width of the argument to $getpattern must be the same as the width +of the object(s) on the left-hand side of the assignment statement. + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3080: +An invalid format specifier was detected in the first argument to a call +to $value$plusargs. The valid format specifiers are: + b, B, d, D, e, E, f, F, g, G, h, H, o, O, s, S, x, X. + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3081: +The first argument to $value$plusargs must be a string that is used +both for locating the plusarg and for formatting the value. + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3082: +The second argument to $value$plusargs must be a modifiable variable +object capable of receiving a value formatted according to the format +specifier in the first argument. + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3083: +An attempt was made to write to a read-only file. + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3084: +The specified argument to the specified system task/function must be a +valid file descriptor. (The left-most bit of the file descriptor must be +set.) + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3085: +The specified argument to the specified system task or function is not +recognized as an open file descriptor. + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3086: +The third argument to $fseek() specifies how to set the position of the +next input or output operation on the file. This value must be one of +the following: + 0 - set position equal to offset bytes + 1 - set position to current location plus offset + 2 - set position to EOF plus offset + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3087: +An unexpected format character was encountered in a formatted string +argument to the specified system task or function. +Valid format characters are: + b, B, c, C, d, D, e, E, f, F, g, G, h, H, m, M, + o, O, s, S, t, T, u, U, v, V, x, X, z, Z, % + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3088: +An unexpected file mode was passed to the specified system task or +function. Valid file modes are: + a, a+, a+b, ab, ab+, r, r+, r+b, rb, rb+, w, w+, w+b, wb, wb+ + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3089: +The memory (1st) argument to the specified PLA system task must have an +ascending range. + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3090: +The number of PLA inputs listed in the second argument to the specified +PLA system task must be less than or equal to the size of the memory word. + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3091: +The number of PLA outputs listed in the third argument to the specified +PLA system task must be less than or equal to the number of memory words. + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3092: +The start (2nd) argument of the specified system function must be less +than the end (3rd) argument. The start value will be returned as output. + + +vsim Message # 3093: +The mean argument to the specified system function must be greater than +zero. It is an integer input that causes the average value returned by +the function to approach the value specified. + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3094: +The degree of freedom argument to the specified system function must be +greater than zero. It is an integer input that helps determine the shape +of the density function. Larger numbers will spread the returned values +over a wider range. + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3095: +The k_stage argument to the specified system function must be greater +than zero. + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3096: +The first argument to $countdrivers must be a scalar net or a bit-select +of a vector net. + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3097: +The specified argument to $countdrivers must be an integer object into +which a value can be written. + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3098: +The specified argument to the specified system task must be a memory +object. + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3099: +The first argument to $sdf_annotate must be a filename represented as a +character string literal or a reg containing a character string naming +the file to be opened. + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3100: +The optional second argument to $sdf_annotate, if specified, must +specify the scope to which to annotate the information in the SDF file. +The SDF annotator uses the hierarchy level of the specified instance for +running the annotation. Array indices are permitted. If the module +instance is not specified, the SDF Annotator uses the module containing +the call to the $sdf_annotate system task as the module instance for +annotation. + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3101: +The optional third argument to $sdf_annotate, if specified, must be a +character string that provides the name of a configuration file. +Information in this file can be used to provide detailed control over +many aspects of annotation. + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3102: +The optional fourth argument to $sdf_annotate, if specified, must be a +character string that provides the name of the log file used during SDF +annotation. Each individual annotation of timing data from the SDF file +results in an entry in the log file. + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3103: +The optional fifth argument to $sdf_annotate, if specified, must be a +character string specifying which member of the min/typ/max triples will +be annotated. The legal values for this string are: MINIMUM, TYPICAL, +MAXIMUM, TOOL_CONTROL (default). This overrides any MTM_SPEC keywords +in the configuration file. + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3104: +The optional sixth argument to $sdf_annotate, if specified, must be a +character string specifying the non-negative scale factors to be used +while annotating timing values. For example, "1.6:1.4:1.2" causes +minimum values to be multiplied by 1.6, typical values by 1.4, and +maximum values by 1.2. The default values are 1.0:1.0:1.0. The scale +factors argument overrides any SCALE_FACTORS keywords in the +configuration file. + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3105: +The optional seventh argument to $sdf_annotate, if specified, must be a +character string specifying how the scale factors should be applied to +the min/typ/max triples. The legal values for this string are: +FROM_MINIMUM, FROM_TYPICAL, FROM_MAXIMUM, FROM_MTM (default). This +overrides any SCALE_TYPE keywords in the configuration file. + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3106: +The file_pathname argument to the specified system task can be a double +quoted pathname (literal string), a reg type variable, or an expression +that denotes the file pathname. + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3107: +A file with the specified name has already been opened and is in use. + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3108: +The specified system task requires a filename argument. + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3109: +The specified argument to the specified system task must be a filename. +The argument can be a literal string or a variable or expression that +can be interpreted as a string. + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3110: +$dumpfile() can be called only once to open a dump file whereas +$fdumpfile() can be called to open any number of dumpfiles. + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3111: +The last argument to the specified system task must be a filename. + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3112: +$dumplimit() requires only one argument that is a file size. It +specifies the maximum size of the VCD file in bytes. When the size of +the VCD file reaches this number of bytes, the dumping stops and a +comment is inserted into the VCD file indicating that the dump limit +was reached. + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3113: +The first n-1 arguments to $dumpports() must be module identifiers. +Only modules are allowed (not variables). If more than one module +identifier is specified, they must be separated by commas. Pathnames +to modules are allowed using the period hierarchy separator. Literal +strings are not allowed for the module identifier. If no module +identifiers are specified, the scope is the module from which +$dumpports() is called. + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3114: +An unknown file was passed to one of the $dumpports system tasks. This +message can occur if $dumpportson(), $dumpportsoff(), $dumpportsall(), +or $dumpportsflush() is called without first calling $dumpports() with +the specified filename. + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3115: +Dynamic loading of the specified file did not succeed. There might be an +additional message from the loader indicating the problem. Verify that +the full path to the file is correct and that the file is marked as +readable. Also verify that the object file was compiled and linked on +the same type of platform as the QuestaSim that is trying to load it. +"Same type of platform" means not only HP, Solaris, etc., but also +32-bit versus 64-bit. 32-bit QuestaSim can load only 32-bit shared +libraries and 64-bit QuestaSim can load only 64-bit shared libraries. +On Solaris, you might need to set the LD_LIBRARY_PATH environment variable. + + +vsim Message # 3116: +A problem occurred while trying to read symbols from a dynamically +loaded object file. Verify that the object file was compiled and linked +on the same type of platform as the QuestaSim that is trying to load it. +This message might be followed by another message that gives more +information about the problem. + + +vsim Message # 3117: +The simulator does not contain the information necessary to support +the acc_handle_datapath() function. + + +vsim Message # 3118: +The checkpoint command requires a filename or a directory argument. If the +argument represents a preexisting directory or is specified with the '-dir' +option, then a checkpoint file named 'vsim.cpt' is created in that directory. + + +vsim Message # 3119: +A problem occurred when trying to open the GUI checkpoint command file. +The effect is that virtuals will not be saved in the checkpoint file. + + +vsim Message # 3120: +A problem occurred while copying the GUI checkpoint command file into +the checkpoint file. + + +vsim Message # 3121: +For the matching ordering operators applied to operands of type +STD_ULOGIC, if either operand is the value '-', an error is reported in +a manner equivalent to execution of the following assertion statement +(see 10.3): + assert FALSE + report "STD_LOGIC_1164: '-' operand for matching ordering operator" + severity ERROR; + +[DOC: IEEE Std 1076-2008 VHDL LRM - 9.2.3 Relational operators] + + +vsim Message # 3122: +The foreign architecture mentioned does not contain save/restore callbacks. +This means that the state of those foreign architecture will not be +saved in the checkpoint file and can not be restored later. + + +vsim Message # 3123: +An unrecoverable error occurred during the checkpoint process; +therefore, checkpointing is aborted and no checkpoint file is written. + + +vsim Message # 3124: +The value ranges of a formal port and the actual to which it is +connected must intersect. For example, a formal port whose value range +is 1 to 5 cannot be connected to an actual signal whose value range is +6 to 10. + + +vsim Message # 3125: +The file supplied for the checkpoint command could not be removed +to allow it to be over-written. The error should contain additional +information from the system as to why the failure occurred. + + +vsim Message # 3126: +The file supplied for the checkpoint command could not be over-written +since it is in use from a currently active "restore". A different name +for the new checkpoint file must be given. + + +vsim Message # 3127: +The specified code coverage exclusion file could not be opened for +reading. Verify that the path to the file exists and that the file +permissions allow reading. + + +vsim Message # 3128: +Parallel simulator does not support $countdrivers() for cross-partition nets. The +value returned will be the number of drivers contained within the partition +from which $countdrivers was called. + + +vsim Message # 3129: +The specified value is not a valid line number. + + +vsim Message # 3130: +A veriusertfs entry does not contain a task/function name. This entry +is ignored. The tfname field of an s_tfcell data structure must contain +a system task/function name in order for the callback functions to be +matched to a system task/function call in Verilog code. See veriuser.h +for a description of the s_tfcell data structure. + + +vsim Message # 3131: +A NULL region ID was passed to the specified function. The region ID +parameter is required. +[DOC: QuestaSim Foreign Language Interface Manual] + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3132: +A NULL process ID was passed to the specified function. The process ID +parameter is required. +[DOC: QuestaSim Foreign Language Interface Manual] + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3133: +A NULL signal ID was passed to the specified function. The signal ID +parameter is required. +[DOC: QuestaSim Foreign Language Interface Manual] + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3134: +A NULL driver ID was passed to the specified function. The driver ID +parameter is required. +[DOC: QuestaSim Foreign Language Interface Manual] + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3135: +A NULL type ID was passed to the specified function. The type ID +parameter is required. +[DOC: QuestaSim Foreign Language Interface Manual] + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3136: +A NULL variable ID was passed to the specified function. The variable ID +parameter is required. +[DOC: QuestaSim Foreign Language Interface Manual] + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3137: +A NULL function pointer was passed to the specified function. The +function pointer parameter is required. +[DOC: QuestaSim Foreign Language Interface Manual] + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3138: +A NULL time pointer was passed to the specified function. The time +pointer parameter is required. +[DOC: QuestaSim Foreign Language Interface Manual] + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3139: +A NULL char pointer was passed to the specified function. The char +pointer parameter is required. +[DOC: QuestaSim Foreign Language Interface Manual] + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3140: +A NULL name was passed to the specified function. The name parameter +is required. +[DOC: QuestaSim Foreign Language Interface Manual] + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3141: +A NULL or empty library name string was passed to mti_LoadRegion(). +The library name parameter is required. + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3142: +A NULL or empty design unit name string was passed to mti_LoadRegion(). +The design unit name parameter is required. + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3143: +The specified instance name (5th parameter to mti_LoadRegion()) is +already being used in the requested region (4th parameter). + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3144: +The specified name (1st parameter to mti_CreateProcess()) is already +being used in the current context. + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3145: +The specified priority is invalid. Please see +/modeltech/include/mti.h for valid priority values. + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3146: +The specified name (1st parameter to mti_CreateProcessWithPriority()) +is already being used in the current context. + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3147: +A problem occurred when trying to restore the requested process. This +can occur if the name passed to mti_RestoreProcess() does not match the +name used when the process was originally created. It can also occur if +internal data for the process is missing. +[DOC: QuestaSim Foreign Language Interface Manual - mti_RestoreProcess()] + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3148: +An invalid force type was passed to mti_ForceSignal(). Please see +/modeltech/include/mti.h for the valid force types. + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3149: +The specified problem occurred during the actual forcing or releasing of +the signal. + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3150: +mti_GetArrayVarValue() or mti_GetVarValueIndirect() cannot be used to get +the value of a record variable. +[DOC: QuestaSim Foreign Language Interface Manual - mti_GetArrayVarValue() +or mti_GetVarValueIndirect()] + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3151: +mti_GetVarAddr() cannot be used to get the address of a record variable. +[DOC: QuestaSim Foreign Language Interface Manual - mti_GetVarAddr()] + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3152: +mti_SetVarValue() cannot be used to set the value of a record variable. +[DOC: QuestaSim Foreign Language Interface Manual - mti_SetVarValue()] + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3153: +A NULL value pointer was passed to mti_Image(). The value pointer +parameter is required. +[DOC: QuestaSim Foreign Language Interface Manual - mti_Image()] + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3154: +A NULL function pointer was passed to the specified function. +The function pointer parameter is required. +[DOC: QuestaSim Foreign Language Interface Manual] + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3155: +The FLI is not available in the PE version of the product. + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3156: +A NULL command was passed to mti_SetCmdIntercepts(). The command +parameter is required. +[DOC: QuestaSim Foreign Language Interface Manual - mti_SetCmdIntercepts()] + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3157: +An invalid command was passed to mti_SetCmdIntercepts(). +[DOC: QuestaSim Foreign Language Interface Manual - mti_SetCmdIntercepts()] + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3158: +A NULL section name was passed to mti_FindProjectEntry(). The section +name parameter is required. +[DOC: QuestaSim Foreign Language Interface Manual - mti_FindProjectEntry()] + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3159: +The specified foreign initialization function could not be found in the +specified object file. Verify that the initialization function name is +spelled correctly and that this object file is supposed to contain this +function. + + +vsim Message # 3160: +An error occurred when trying to load the specified object file. Verify +that the object file exists and that you have read permission. Also, if +the foreign attribute that refers to the object file contains a reference +to an environment variable, make sure the environment variable has a value. +[DOC: QuestaSim Foreign Language Interface Manual - Using the VHDL FLI Section] + + +vsim Message # 3161: +A foreign attribute must contain the name of an initialization function +and the name of a shared library. +[DOC: QuestaSim Foreign Language Interface Manual] + + +vsim Message # 3162: +A foreign attribute must contain the name of an initialization function +and the name of one shared library. Optional parameters can follow a +semi-colon (;). +[DOC: QuestaSim Foreign Language Interface Manual] + + +vsim Message # 3163: +The user interface force command uses the semantics of Verilog where +a wire is global to the design, while the VHDL force statement uses the +semantics of VHDL where a port is a signal local to its position in the +design hierarchy. + + +vsim Message # 3164: +A NULL signal name was passed to mti_GetDrivingSignals(). The signal +name parameter is required. +[DOC: QuestaSim Foreign Language Interface Manual - mti_GetDrivingSignals()] + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3165: +An invalid signal name was passed to mti_GetDrivingSignals(). Verify +that the signal name is spelled correctly and that the signal exists in +the design. + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3166: +The specified object file was loaded more than once. Verify that this +was intentional because the behavior of global data structures could be +not as expected. + + +vsim Message # 3167: +The LMC_HOME environment variable must be set to the root of the +SmartModel Library installation directory when using the vsim option -lmc. + + +vsim Message # 3168: +A problem occurred while trying to find the specified symbol in a +dynamically loaded object file. + + +vsim Message # 3169: +Changed package bodies are not automatically reloaded because all +generated code that depends upon a package uses type and constant +information directly out of the package body as part of the generated +code. Reloading a package body would corrupt all generated code that +uses the package body; therefore, the entire design must be reloaded. + + +vsim Message # 3170: +The specified design unit could not be found for loading. Verify that +the design unit has been compiled into the correct library and that the +library is mapped correctly. (Check the modelsim.ini file.) The vlib +command creates QuestaSim libraries and the vmap command maps them. + + +vsim Message # 3171: +The compiled machine code for the specified design unit could not be +found for loading. Verify that the design unit has been compiled into +the correct library and that the library is mapped correctly. (Check the +modelsim.ini file.) The vlib command creates QuestaSim libraries and the +vmap command maps them. + + +vsim Message # 3172: +Once a module is optimized its parameters become frozen. If the current +design being loaded attempts to instantiate that module with a different +set of parameters, it will fail. The module must be reoptimized with +the new set of parameters. + + +vsim Message # 3173: +No architectures could be found for the specified entity. Verify that +the entity has been compiled into the correct library, that at least one +architecture of it has been compiled into the (same) library, and that +the library is mapped correctly. (Use the vmap command to check the +modelsim.ini file.) The vlib command is used to create a library, and +the vmap command is used to create a logical library name for it. + + +vsim Message # 3174: +A package that contains certain kinds of declarations like procedures, +functions, or deferred constants requires a package body to complete +its definition. Verify that the package declaration and its body have +each been compiled into the same, correct library, and that the library +has been mapped correctly. (Use the vmap command to check the +modelsim.ini file.) The vlib command is used to create a library, and +the vmap command is used to create a logical library name for it. + +If you get this message for the std.STANDARD package, which actually has +no body and does not require one, then the installation has probably +been corrupted. You may need to uninstall and reinstall QuestaSim. + + +vsim Message # 3175: +A problem occurred while trying to open the specified file. Verify that +the path exists and that you have write permission in the directory. +The assert file is controlled by either the -assertfile option to vsim +or the AssertFile variable in the modelsim.ini file. + + +vsim Message # 3176: +The number provided to the step command must be an integer. The usage +of the command should be displayed after the error message. +[DOC: QuestaSim Command Reference - step command] + + +vsim Message # 3177: +The restore command requires a filename or a directory argument. If the +specified argument represents a preexisting directory, then a checkpoint file +named 'vsim.cpt' is expected to be found in that directory. + + +vsim Message # 3178: +The checkpoint file is either invalid or corrupted. Verify that the +specified file path points to a checkpoint file. +Checkpoint files must be created and used in the same environment. +The same environment means the same hardware platform, the same OS +and patch version, and the same version of any PLI/FLI code loaded +in the simulation. + + +vsim Message # 3179: +This is not an error, but an unexpected usage. We presume the force +mode would be consistent for a particular signal. + + +vsim Message # 3180: +When attempting to restore the state of a previous simulation an +unrecoverable problem occurred. (This is an internal error and should +not normally occur.) + + +vsim Message # 3181: +The simulator was unable to allocate the required amount of memory in +the required location during a restore operation. Verify that the +restore is being done on the same type of machine that created the +checkpoint file. + +** LINUX NOTE ** + +On certain LINUX versions the restore functionality may occasionally +fail. This is due to certain memory allocation security +(anti-hacking) feature of LINUX. The following are the known issues and the workarounds: + +* Redhat Enterprise release v.3 update3 was the first version to have exec-shield feature. +There are several methods available to disable this feature and to +allow restore to work again. + +To turn it off temporarily give the commands: + + sysctl -w kernel.exec-shield=0 + or + echo 0 > /proc/sys/kernel/exec-shield + +Alternatively, to turn it off permanently put this in your +/etc/sysctl.conf file: + + kernel.exec-shield=0 + +(Note these require administrator or root access.) + +To turn the feature off for a single invocation of vsim use the +"setarch" program to invoke vsim, like this: + + setarch i686 vsim [options]... + +* SUSE Enterprise Server 10 has a security feature related to address space randomization. + +There are several methods available to disable this feature and to +allow restore to work again. + +To turn it off temporarily give the commands: + + sysctl -w kernel.randomize_va_space=0 + or + echo 0 > /proc/sys/kernel/randomize_va_space + +Alternatively, to turn it off permanently put this in your +/etc/sysctl.conf file: + + kernel.randomize_va_space=0 + +(Note these require administrator or root access.) + + +vsim Message # 3182: +A checkpoint file that was not created during the current session of +vsim cannot be restored with the restore command. Instead, you must quit +vsim and reinvoke it with the -restore option. + + +vsim Message # 3183: +A checkpoint file must be loaded into the same version of the simulator +that wrote it. + + +vsim Message # 3184: +A checkpoint file must be restored on the same platform type on which +it was created. + + +vsim Message # 3185: +The number of bytes logged as written to a checkpoint file does not +match the number of bytes read from the checkpoint file during the +specified restore phase. A mismatch often indicates reading out of +position, because the saves call backs did not match the restore +call backs. + + +vsim Message # 3186: +Restore of the simulation failed do to a licensing error. + + +vsim Message # 3187: +The time resolution taken from the checkpoint file is not compatible +with the time resolution with which the simulator was invoked. In order +to restore the checkpoint file, reinvoke the simulator with an appropriate +time resolution. + + +vsim Message # 3188: +An attempt to open the specified user file that was open when the +checkpoint file was created failed. Verify that the file path is valid +and that file permissions are set for proper access. + + +vsim Message # 3189: +A user file that was open for write or append and that was not empty +when the checkpoint file was created could not be found or otherwise +opened during the restore operation. The simulator will attempt to +recreate the file in write mode and reposition it to its former position. +The original file contents cannot be restored. + + +vsim Message # 3190: +There was a problem positioning the specified file to the position where +it was at the time of the checkpoint. + + +vsim Message # 3191: +There was a problem creating the GUI restore command file. This means +that the GUI might not come up in the same state that it was in when the +checkpoint was created. Verify that the file path exists and that you +have write permission in the directory. + + +vsim Message # 3192: +The -fast compiled secondary might have been deleted from the library, +or a subsequent compilation of a different module having the same name +might have purged the library of the -fast compiled secondaries for that +module. + + +vsim Message # 3193: +Dynamic loading of the specified file did not succeed. Verify that the +full path to the file is correct and that the file is marked as readable. +Also verify that the object file was compiled and linked on the same type +of platform as the QuestaSim that is trying to load it. + + +vsim Message # 3194: +The delay scale specified with the vsim options -sdfmin, -sdftyp, and +-sdfmax must be a real number. +For example: + vsim -sdfmin@0.5 test11.sdf top + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3195: +An @ symbol was detected in an -sdfmin, -sdftyp, or -sdfmax vsim option +but it was not followed by a delay scale. The delay scale specified with +the vsim options -sdfmin, -sdftyp, and -sdfmax must be a real number. +For example: + vsim -sdfmin@0.5 test11.sdf top + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3196: +An SDF file specified with an -sdfmin, -sdftyp, or -sdfmax vsim option +could not be found. Verify that the file exists and that you have the +correct permissions to access the file. + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3197: +Dynamic loading of the specified file did not succeed. Verify that the +full path to the file is correct and that the file is marked as readable. +Also verify that the object file was compiled and linked on the same +type of platform as the vsim that is trying to load it. i.e. A 32-bit vsim +can load only 32-bit shared libraries and a 64-bit vsim can load only 64-bit +shared libraries. On non-Windows platforms you should check that the +LD_LIBRARY_PATH environment variable is set correctly. + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3198: +Unloading of a dynamically loaded shared object did not succeed for the +specified reason. + + +vsim Message # 3199: +An unexpected error occurred while processing the Load Complete callback +list at the end of the loading phase. + + +vsim Message # 3200: +An unexpected error occurred while processing the Restore Complete +callback list at the end of the restore phase. + + +vsim Message # 3201: +The specified Tcl init file could not be opened. Verify that the file +path exists and that you have read permission. + + +vsim Message # 3202: +The signal connected to the specified port has a type conversion or +conversion function in the port map. This cannot be supported with the +-dumpports functionality. + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3203: +When dumping a VHDL VCD file with the -dumpports option, the signal +connected to an INOUT port must be a std_ulogic or vl_ulogic type or +subtype of std_ulogic or vl_ulogic. + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3204: +If you are trying to generate a VCD file for a Verilog design and +resimulate it then you have most likely used the wrong vcd commands. +Here are the correct procedures to generate and resimulate a Verilog +design with a VCD file: + + vsim + vcd dumpports -file + run -all + quit -f + vsim -vcdstim + run -all + +Note that the VCD file format created with dumpports is not the correct +format for the -vcdread option. + +Here are the correct procedures to generate a VCD file from a VHDL +design that can be resimulated with the -vcdread option: + + vsim + splitio + vcd file -nomap -direction + vcd add -ports /* + run -all + quit -sim + vsim -vcdread dump.vcd + run -all + +[DOC: QuestaSim Command Reference - splitio, vcd, and vsim commands] + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3205: +When using the vsim option -vcdread, the top level design unit must +be a VHDL entity/architecture. When using the vsim option -vcdstim, the +top level design unit must be either a VHDL entity/architecture or a +Verilog module. +[DOC: QuestaSim Command Reference - vsim command] + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3206: +The specified port that appears in the VCD file cannot be found in +the top-level design unit. Verify that the correct VCD file is being +applied to the design. + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3207: +If you are trying to generate a VCD file for a VHDL, Verilog, or mixed +HDL design, and resimulate it, then you have most likely used the wrong +vcd commands. +[DOC: QuestaSim User's Manual - Value Change Dump (VCD) Files Chapter] + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3208: +The VCD parser encountered the end of the VCD file while it was looking +for a token. Check the VCD file to make sure that its format is valid. + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3209: +The VCD parser encountered the specified character instead of the +'$' that it was expecting when attempting to read a VCD command. + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3210: +An unexpected command was encountered in the VCD file. +The valid commands are: + $comment $date $dumpall $dumpoff $dumpon + $dumpports $dumpvars $end $enddefinitions $scope + $timescale $upscope $var $vcdclose $version + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3211: +The VCD parser encountered the specified character instead of +the numeric digit that it was expecting. + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3212: +The VCD parser encountered the specified timescale number instead +of the 1, 10, or 100 that it was expecting. The timescale must be +specified as 1, 10 or 100 followed by a time unit that is one of: +fs, ps, ns, us, ms, or s. + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3213: +The VCD parser encountered the specified timescale unit instead +of the valid timescale unit that is was expecting. The timescale +must be specified as 1, 10 or 100 followed by a time unit that is +one of: fs, ps, ns, us, ms, or s. + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3214: +The VCD timescale must be greater than or equal to the simulator +time resolution. + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3215: +The width of a port in a $var statement must be 1. + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3216: +An unexpected command was encountered in the definition section of +the VCD file. The valid commands are: + $comment $date $enddefinitions $scope $timescale + $upscope $version $vcdclose $var + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3217: +A port of type std_logic can have only the following values: + U, X, 0, 1, Z, W, L, H, - + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3218: +A port of type bit can have only the following values: 0, 1. + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3219: +The valid extended VCD port values are: + D Input low + d Input low (two or more drivers active) + 0 Input and output are driving low + U Input high + u Input high (two or more drivers active) + 1 Input and output are driving high + N Input unknown + Z Input tri-state + F Input and output unconnected + f Input and output tri-state + L Output low + l Output low (two or more drivers active) + H Output high + h Output high (two or more drivers active) + X Output unknown + T Output tri-state + A Unknown (input driving low, output driving high) + a Unknown (input driving low, output driving unknown) + B Unknown (input driving high, output driving low) + b Unknown (input driving high, output driving unknown) + C Unknown (input driving unknown, output driving low) + c Unknown (input driving unknown, output driving high) + ? Unknown +[DOC: QuestaSim User's Manual - Value Change Dump (VCD) Files Chapter] + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3220: +While resimulating from a VCD file, a $dumpoff command was encountered. +This command cannot be simulated and since there will be data missing +beyond this point because of the $dumpoff resimulation is stopped. + +This error message can be suppressed or downgraded to a note or warning. + +vsim Message # 3221: +The expected VCD simulation commands are: + $comment $dumpall $dumpon $dumpports + $dumpvars $end $vcdclose #