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Updated cdc_strobe. Used gray counter under the hood
This commit is contained in:
Konstantin Pavlov
parent
261e0565cf
commit
0e19b10433
135
cdc_strobe.sv
135
cdc_strobe.sv
@ -1,94 +1,105 @@
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//--------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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// cdc_strobe.sv
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// Konstantin Pavlov, pavlovconst@gmail.com
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//--------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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// INFO --------------------------------------------------------------------------------
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// INFO ------------------------------------------------------------------------
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// Clock crossing setup for single-pulse strobes
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// CDC stands for "clock data crossing"
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// Strobes could trigger transfers of almost-static data between clock doamins
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//
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// This is a simplest form of strobe CDC circuit. Good enough for rare single
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// strobe events. This module does NOT support close-standing strobes,
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// placed in adjacent lock cycles
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// - Maximum input strobe rate is every second clk1 clock cycle
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//
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// Don`t forget to write false_path constraints for all your synchronizers
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// The best way to do it - is to mark all synchonizer delay.sv instances
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// with "_SYNC_ATTR" suffix. After that, just one constraint is required:
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// - Input strobe may span several clock cycles, but it will be considered one
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// event and only one single-cycle strobe will be generated to the output
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//
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// - When clk2 is essentially less than clk1 it is possible that strb2 will
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// remain HIGH for several consecutive clk2 cycles. On the output every
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// HIGH cycle should be considered as a separate strobe event
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//
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// - When clk2 is essentially less than clk1 - output strobes could even
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// "overlap" or miss. In this case, please restrict input strobe event rate
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//
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// - cdc_strobe module features a 2 clock cycles propagation delay
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//
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//
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//
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// False_path constraint is required from all nodes with "_FP_ATTR" suffix
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//
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// For Quartus:
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// set_false_path -to [get_registers {*delay:*_SYNC_ATTR*|data[1]*}]
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// set_false_path -from [get_registers {*_FP_ATTR*}]
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//
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// For Vivado:
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// set_false_path -to [get_cells -hier -filter {NAME =~ *_SYNC_ATTR/data_reg[1]*}]
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// set_false_path -from [get_cells -hier -filter {NAME =~ *_FP_ATTR*}]
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//
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/* --- INSTANTIATION TEMPLATE BEGIN ---
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cdc_strobe CS [7:0] (
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.clk1_i( {8{clk1}} ),
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.nrst1_i( {8{1'b1}} ),
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.strb1_i( input_strobes[7:0] ),
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cdc_strobe_v2 cdc_wr_req (
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.arst( 1'b0 ),
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.clk2_i( {8{clk2}} ),
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.strb2_o( output_strobes[7:0] )
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.clk1( clk1 ),
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.nrst1( 1'b1 ),
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.strb1( wr_req_clk1 ),
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.clk2( {8{clk2}} ),
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.nrst2( 1'b1 ),
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.strb2( wr_req_clk2 )
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);
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--- INSTANTIATION TEMPLATE END ---*/
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module cdc_strobe #( parameter
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PRE_STRETCH( 2 ) // number of cycles to stretch input strobe
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)(
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input clk1_i, // clock domain 1 clock
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input nrst1_i, // clock domain 1 reset (inversed)
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input strb1_i, // clock domain 1 strobe
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module cdc_strobe (
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input arst, // async reset
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input clk2_i, // clock domain 2 clock
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output strb2_o // clock domain 2 strobe
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input clk1, // clock domain 1 clock
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input nrst1, // clock domain 1 reset (inversed)
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input strb1, // clock domain 1 strobe
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input clk2, // clock domain 2 clock
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input nrst2, // clock domain 2 reset (inversed)
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output strb2 // clock domain 2 strobe
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);
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// This signal should be at_least(!!!) one clk2_i period long
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// Preliminary stretching is usually nessesary, unless you are crossing
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// to essentialy high-frequency clock clk2_i, that is > 2*clk1_i
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logic strb1_stretched;
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// buffering strb1
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logic strb1_b = 1'b0;
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always @(posedge clk1 or posedge arst) begin
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if( arst || ~nrst1 ) begin
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strb1_b <= '0;
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end else begin
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strb1_b <= strb1;
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end
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end
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pulse_stretch #(
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.WIDTH( PRE_STRETCH ),
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.USE_CNTR( 0 )
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) stretch_strb1 (
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.clk( clk1_i ),
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.nrst( nrst1_i ),
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.in( strb1_i ),
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.out( strb1_stretched )
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);
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// strb1 edge detector
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// prevents secondary strobe generation in case strb1 is not one-cycle-high
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logic strb1_ed;
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assign strb1_ed = (~strb1_b && strb1) && ~arst;
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// This is a synchronized signal in clk2_i clock domain,
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// but no guarantee, that it is one-cycle-high
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logic strb2_stretched;
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delay #(
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.LENGTH( 2 ),
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.WIDTH( 1 ),
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.TYPE( "CELLS" ),
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.REGISTER_OUTPUTS( "FALSE" )
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) delay_strb1_SYNC_ATTR (
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.clk( clk2_i ),
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.nrst( 1'b1 ),
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.ena( 1'b1 ),
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// 2 bit gray counter, it must NEVER be reset
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logic [1:0] gc_FP_ATTR = '0;
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always @(posedge clk1) begin
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if( strb1_ed ) begin
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gc_FP_ATTR[1:0] <= {gc_FP_ATTR[0],~gc_FP_ATTR[1]}; // incrementing counter
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end
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end
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.in( strb1_stretched ),
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.out( strb2_stretched )
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);
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// buffering counter value on clk2
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// gray counter does not need a synchronizer
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logic [1:0][1:0] gc_b = '0;
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always @(posedge clk2 or posedge arst) begin
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if( arst || ~nrst2 ) begin
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gc_b[1:0] <= {2{gc_FP_ATTR[1:0]}};
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end else begin
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gc_b[1:0] <= {gc_b[0],gc_FP_ATTR[1:0]}; // shifting left
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end
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end
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// gray_bit_b edge detector
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assign strb2 = (gc_b[1][1:0] != gc_b[0][1:0] ) && ~arst;
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edge_detect ed_strb2 (
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.clk( clk2_i ),
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.nrst( 1'b1 ),
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.in( strb2_stretched ),
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.rising( strb2_o ), // and now the signal is definitely one-cycle-high
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.falling( ),
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.both( )
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);
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endmodule
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143
cdc_strobe_tb.sv
Executable file
143
cdc_strobe_tb.sv
Executable file
@ -0,0 +1,143 @@
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//------------------------------------------------------------------------------
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// moving_average_tb.sv
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// Konstantin Pavlov, pavlovconst@gmail.com
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//------------------------------------------------------------------------------
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// INFO ------------------------------------------------------------------------
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// testbench for cdc_strobe.sv module
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//
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`timescale 1ns / 1ps
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module cdc_strobe_tb();
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logic clk200;
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initial begin
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#0 clk200 = 1'b0;
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forever
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#2.5 clk200 = ~clk200;
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end
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// external device "asynchronous" clock
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logic clk33a;
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initial begin
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#0 clk33a = 1'b0;
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forever
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#7 clk33a = ~clk33a;
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end
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logic clk33;
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//assign clk33 = clk33a;
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always @(*) begin
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clk33 = #($urandom_range(0, 2000)*1ps) clk33a;
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end
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logic rst;
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initial begin
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#0 rst = 1'b0;
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#10.2 rst = 1'b1;
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#5 rst = 1'b0;
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//#10000;
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forever begin
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#9985 rst = ~rst;
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#5 rst = ~rst;
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end
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end
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logic nrst;
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assign nrst = ~rst;
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logic rst_once;
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initial begin
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#0 rst_once = 1'b0;
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#10.2 rst_once = 1'b1;
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#5 rst_once = 1'b0;
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end
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logic nrst_once;
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assign nrst_once = ~rst_once;
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logic [31:0] DerivedClocks;
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clk_divider #(
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.WIDTH( 32 )
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) cd1 (
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.clk( clk200 ),
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.nrst( nrst_once ),
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.ena( 1'b1 ),
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.out( DerivedClocks[31:0] )
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);
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logic [31:0] E_DerivedClocks;
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edge_detect ed1[31:0] (
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.clk( {32{clk200}} ),
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.nrst( {32{nrst_once}} ),
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.in( DerivedClocks[31:0] ),
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.rising( E_DerivedClocks[31:0] ),
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.falling( ),
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.both( )
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);
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logic [15:0] RandomNumber1;
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c_rand rng1 (
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.clk(clk200),
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.rst(rst_once),
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.reseed(1'b0),
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.seed_val(DerivedClocks[31:0]),
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.out( RandomNumber1[15:0] )
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);
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logic start;
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initial begin
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#0 start = 1'b0;
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#100 start = 1'b1;
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#20 start = 1'b0;
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end
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// Module under test ==========================================================
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logic strb1s;
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assign strb1s = |RandomNumber1[2:1];
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/*logic strb1s = 1'b0;
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always_ff @(posedge clk200) begin
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strb1s <= ~strb1s;
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end
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*/
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logic strb1;
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edge_detect ed_strb1 (
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.clk( clk200 ),
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.nrst( nrst_once ),
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.in( strb1s ),
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.rising( strb1 ),
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.falling( ),
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.both( )
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);
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logic strb2;
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cdc_strobe M (
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.arst( 1'b0 ),
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.clk1( clk200 ),
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.nrst1( nrst_once ),
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.strb1( strb1 ),
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.clk2( clk33 ),
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.nrst2( 1'b1 ),
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.strb2( strb2 )
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);
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logic [7:0] strb1_cntr = '0;
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always_ff @(posedge clk200) begin
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if( strb1 ) begin
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strb1_cntr[7:0] <= strb1_cntr[7:0] + 1'b1;
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end
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end
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logic [7:0] strb2_cntr = '0;
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always_ff @(posedge clk33) begin
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if( strb2 ) begin
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strb2_cntr[7:0] <= strb2_cntr[7:0] + 1'b1;
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end
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end
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endmodule
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