Added quartus benchmarking project

example_projects/quartus_benchmark/dynamic_delay.sv

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+//--------------------------------------------------------------------------------
+// dynamic_delay.v
+// Konstantin Pavlov, pavlovconst@gmail.com
+//--------------------------------------------------------------------------------
+
+// INFO --------------------------------------------------------------------------------
+//  Dynamic delay for arbitrary signal
+//
+//  CAUTION: The module intentionally does NOT implement error handling when
+//           LENGTH is not a multiple of 2. Please handle "out of range"
+//           checks externally.
+
+
+/* --- INSTANTIATION TEMPLATE BEGIN ---
+
+dynamic_delay #(
+  .LENGTH( 8 )
+  //.SEL_W( 3 )
+) DD1 (
+  .clk( clk ),
+  .nrst( 1'b1 ),
+  .ena( 1'b1 ),
+  .in(  ),
+  .sel(  ),
+  .out(  )
+);
+
+--- INSTANTIATION TEMPLATE END ---*/
+
+
+module dynamic_delay #( parameter
+  LENGTH = 8,               // maximum delay chain width
+  SEL_W = $clog2(LENGTH)    // output selector width
+)(
+  input clk,
+  input nrst,
+  input ena,
+  input in,
+  input [SEL_W-1:0] sel,     // output selector
+  output logic out
+);
+
+logic [(LENGTH-1):0] data = 0;
+
+integer i;
+always_ff @(posedge clk) begin
+  if (~nrst) begin
+    data[(LENGTH-1):0] <= 0;
+    out <= 0;
+  end else if (ena) begin
+    data[0] <= in;
+    for (i=1; i<LENGTH; i=i+1) begin
+      data[i] <= data[i-1];
+    end
+    out <= data[sel[SEL_W-1:0]];
+  end
+end
+
+endmodule

example_projects/quartus_benchmark/main.sdc

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+
+# main reference clock, 100 MHz
+create_clock -period 10.000 -waveform { 0.000 5.000 } [get_ports {clk}]
+
+derive_pll_clocks
+derive_clock_uncertainty

example_projects/quartus_benchmark/main.sv

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+//------------------------------------------------------------------------------
+// main.sv
+// Konstantin Pavlov, pavlovconst@gmail.com
+//------------------------------------------------------------------------------
+
+// INFO ------------------------------------------------------------------------
+// Quartus benchmark project
+//
+// This project uses dynamic_delay.sv module to model both high-register count and
+// combinational-intensive design. See "Messages" tab for TOTAL time
+// spent for compilation. This will give you some quantitive charachteristic
+// of your environment processing power
+
+`define WIDTH 16
+`define LENGTH 1024
+`define SEL_W $clog2(`LENGTH)
+
+
+module main(
+
+  input clk,
+  input nrst,
+
+  input [`WIDTH-1:0] id,
+  input [`SEL_W-1:0] sel,
+  output [`WIDTH-1:0] od
+);
+
+dynamic_delay #(
+  .LENGTH( `LENGTH ),
+  .SEL_W( `SEL_W )
+) dd [`WIDTH-1:0] (
+  .clk( {`WIDTH{clk}} ),
+  .nrst( {`WIDTH{nrst}} ),
+  .ena( {`WIDTH{1'b1}} ),
+  .in( id[`WIDTH-1:0] ),
+  .sel( {`WIDTH{sel[`SEL_W-1:0]}} ),
+  .out( od[`WIDTH-1:0] )
+);
+
+endmodule

example_projects/quartus_benchmark/post_flow.tcl

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+#------------------------------------------------------------------------------
+# post_flow.tcl
+# Konstantin Pavlov, pavlovconst@gmail.com
+#------------------------------------------------------------------------------
+
+# INFO ------------------------------------------------------------------------
+# Use this script as a boilerplate for custom reporting or report analisys
+# for Intel Quartus IDE. Your custom messages will be reported in messages window
+# after all normal compilation messages
+#
+# Script requires following QSF assignment
+# set_global_assignment -name PROJECT_OUTPUT_DIRECTORY OUTPUT
+# set_global_assignment -name POST_FLOW_SCRIPT_FILE "quartus_sh:post_flow.tcl"
+
+
+#===============================================================================
+# Set warning on implicit nets declaration
+post_message "=== ERRORS ======================================================="
+set file [open [join [list "./OUTPUT/" [lindex $argv 2] ".map.rpt"] ""] r]
+while {[gets $file line] != -1} {
+  if {[string first "implicit" $line] != -1} {
+    post_message $line
+  }
+}
+close $file
+
+#===============================================================================
+# compuiting elapsed time
+post_message "=== COMPILE TIME ================================================="
+
+set hs 0
+set ms 0
+set ss 0
+set hs_t 0
+set ms_t 0
+set ss_t 0
+
+set file [open [join [list "./OUTPUT/" [lindex $argv 2] ".map.rpt"] ""] r]
+while {[gets $file line] != -1} {
+  set time [string range $line 24 31]
+  if {[string first "Info: Elapsed time:" $line] != -1} {
+    post_message [ join [ list "map:   " $time ] "" ]
+    scan $time "%d:%d:%d" hs ms ss
+    set hs_t [expr {$hs_t + $hs} ]
+    set ms_t [expr {$ms_t + $ms} ]
+    set ss_t [expr {$ss_t + $ss} ]
+  }
+}
+close $file
+
+
+set file [open [join [list "./OUTPUT/" [lindex $argv 2] ".fit.rpt"] ""] r]
+while {[gets $file line] != -1} {
+  set time [string range $line 24 31]
+  if {[string first "Info: Elapsed time:" $line] != -1} {
+    post_message [ join [ list "fit:   " $time ] "" ]
+    scan $time "%d:%d:%d" hs ms ss
+    set hs_t [expr {$hs_t + $hs} ]
+    set ms_t [expr {$ms_t + $ms} ]
+    set ss_t [expr {$ss_t + $ss} ]
+  }
+}
+close $file
+
+
+set file [open [join [list "./OUTPUT/" [lindex $argv 2] ".asm.rpt"] ""] r]
+while {[gets $file line] != -1} {
+  set time [string range $line 24 31]
+  if {[string first "Info: Elapsed time:" $line] != -1} {
+    post_message [ join [ list "asm:   " $time ] "" ]
+    scan $time "%d:%d:%d" hs ms ss
+    set hs_t [expr {$hs_t + $hs} ]
+    set ms_t [expr {$ms_t + $ms} ]
+    set ss_t [expr {$ss_t + $ss} ]
+  }
+}
+close $file
+
+
+set file [open [join [list "./OUTPUT/" [lindex $argv 2] ".sta.rpt"] ""] r]
+while {[gets $file line] != -1} {
+  set time [string range $line 24 31]
+  if {[string first "Info: Elapsed time:" $line] != -1} {
+    post_message [ join [ list "sta:   " $time ] "" ]
+    scan $time "%d:%d:%d" hs ms ss
+    set hs_t [expr {$hs_t + $hs} ]
+    set ms_t [expr {$ms_t + $ms} ]
+    set ss_t [expr {$ss_t + $ss} ]
+  }
+}
+close $file
+
+
+while { $ss_t >= 60 } {
+  set ss_t [expr $ss_t - 60]
+  set ms_t [expr $ms_t + 1]
+}
+while { $ms_t >= 60 } {
+  set ms_t [expr $ms_t - 60]
+  set hs_t [expr $hs_t + 1]
+}
+post_message "----------------------------------"
+post_message [ join [ list "TOTAL: " [format "%02d:%02d:%02d" $hs_t $ms_t $ss_t]] "" ]
+
+
+
+

example_projects/quartus_benchmark/readme.txt

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+
+Quartus benchmark project
+=========================
+
+
+Konstantin Pavlov, pavlovconst@gmail.com
+
+
+This project uses dynamic_delay.sv module to model both high-register count and
+combinational-intensive design.
+
+See Quartus "Messages" tab for TOTAL time spent for compilation. This will give
+you some quantitive charachteristic of your environment processing power.
+
+You can also compare how different machines and environments deal with this
+typical design when compiling for FPGAs. I use only pure RTL code here with
+intention to leave an opportunity to compare compilation time across all
+possible IDE`s and even across all FPGA vendors.
+

example_projects/quartus_benchmark/test.qpf

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+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2017  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel MegaCore Function License Agreement, or other 
+# applicable license agreement, including, without limitation, 
+# that your use is for the sole purpose of programming logic 
+# devices manufactured by Intel and sold by Intel or its 
+# authorized distributors.  Please refer to the applicable 
+# agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 17.0.0 Build 595 04/25/2017 SJ Standard Edition
+# Date created = 11:22:30  September 26, 2018
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "17.0"
+DATE = "11:22:30  September 26, 2018"
+
+# Revisions
+
+PROJECT_REVISION = "test"

example_projects/quartus_benchmark/test.qsf

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+
+set_global_assignment -name FAMILY "Cyclone V"
+set_global_assignment -name DEVICE 5CGXFC4C7F27C8
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.0.0
+set_global_assignment -name LAST_QUARTUS_VERSION "17.0.0 Lite Edition"
+
+set_global_assignment -name TOP_LEVEL_ENTITY main
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY OUTPUT
+set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
+set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
+set_global_assignment -name POST_FLOW_SCRIPT_FILE "quartus_sh:post_flow.tcl"
+
+set_global_assignment -name SYSTEMVERILOG_FILE main.sv
+set_global_assignment -name SYSTEMVERILOG_FILE dynamic_delay.sv
+set_global_assignment -name SDC_FILE main.sdc
+
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+
+
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top