From 1fdc31ad05c8ca0641ee9b635257ef391dfe6579 Mon Sep 17 00:00:00 2001 From: Konstantin Pavlov Date: Mon, 15 Apr 2019 02:37:45 +0300 Subject: [PATCH] Added quartus benchmarking project --- .../quartus_benchmark/dynamic_delay.sv | 59 ++++++++++ example_projects/quartus_benchmark/main.sdc | 6 + example_projects/quartus_benchmark/main.sv | 41 +++++++ .../quartus_benchmark/post_flow.tcl | 107 ++++++++++++++++++ example_projects/quartus_benchmark/readme.txt | 19 ++++ example_projects/quartus_benchmark/test.qpf | 31 +++++ example_projects/quartus_benchmark/test.qsf | 22 ++++ 7 files changed, 285 insertions(+) create mode 100644 example_projects/quartus_benchmark/dynamic_delay.sv create mode 100755 example_projects/quartus_benchmark/main.sdc create mode 100755 example_projects/quartus_benchmark/main.sv create mode 100755 example_projects/quartus_benchmark/post_flow.tcl create mode 100644 example_projects/quartus_benchmark/readme.txt create mode 100755 example_projects/quartus_benchmark/test.qpf create mode 100755 example_projects/quartus_benchmark/test.qsf diff --git a/example_projects/quartus_benchmark/dynamic_delay.sv b/example_projects/quartus_benchmark/dynamic_delay.sv new file mode 100644 index 0000000..4c458ef --- /dev/null +++ b/example_projects/quartus_benchmark/dynamic_delay.sv @@ -0,0 +1,59 @@ +//-------------------------------------------------------------------------------- +// dynamic_delay.v +// Konstantin Pavlov, pavlovconst@gmail.com +//-------------------------------------------------------------------------------- + +// INFO -------------------------------------------------------------------------------- +// Dynamic delay for arbitrary signal +// +// CAUTION: The module intentionally does NOT implement error handling when +// LENGTH is not a multiple of 2. Please handle "out of range" +// checks externally. + + +/* --- INSTANTIATION TEMPLATE BEGIN --- + +dynamic_delay #( + .LENGTH( 8 ) + //.SEL_W( 3 ) +) DD1 ( + .clk( clk ), + .nrst( 1'b1 ), + .ena( 1'b1 ), + .in( ), + .sel( ), + .out( ) +); + +--- INSTANTIATION TEMPLATE END ---*/ + + +module dynamic_delay #( parameter + LENGTH = 8, // maximum delay chain width + SEL_W = $clog2(LENGTH) // output selector width +)( + input clk, + input nrst, + input ena, + input in, + input [SEL_W-1:0] sel, // output selector + output logic out +); + +logic [(LENGTH-1):0] data = 0; + +integer i; +always_ff @(posedge clk) begin + if (~nrst) begin + data[(LENGTH-1):0] <= 0; + out <= 0; + end else if (ena) begin + data[0] <= in; + for (i=1; i= 60 } { + set ss_t [expr $ss_t - 60] + set ms_t [expr $ms_t + 1] +} +while { $ms_t >= 60 } { + set ms_t [expr $ms_t - 60] + set hs_t [expr $hs_t + 1] +} +post_message "----------------------------------" +post_message [ join [ list "TOTAL: " [format "%02d:%02d:%02d" $hs_t $ms_t $ss_t]] "" ] + + + + diff --git a/example_projects/quartus_benchmark/readme.txt b/example_projects/quartus_benchmark/readme.txt new file mode 100644 index 0000000..92f5a3c --- /dev/null +++ b/example_projects/quartus_benchmark/readme.txt @@ -0,0 +1,19 @@ + +Quartus benchmark project +========================= + + +Konstantin Pavlov, pavlovconst@gmail.com + + +This project uses dynamic_delay.sv module to model both high-register count and +combinational-intensive design. + +See Quartus "Messages" tab for TOTAL time spent for compilation. This will give +you some quantitive charachteristic of your environment processing power. + +You can also compare how different machines and environments deal with this +typical design when compiling for FPGAs. I use only pure RTL code here with +intention to leave an opportunity to compare compilation time across all +possible IDE`s and even across all FPGA vendors. + diff --git a/example_projects/quartus_benchmark/test.qpf b/example_projects/quartus_benchmark/test.qpf new file mode 100755 index 0000000..88ba528 --- /dev/null +++ b/example_projects/quartus_benchmark/test.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 17.0.0 Build 595 04/25/2017 SJ Standard Edition +# Date created = 11:22:30 September 26, 2018 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "17.0" +DATE = "11:22:30 September 26, 2018" + +# Revisions + +PROJECT_REVISION = "test" diff --git a/example_projects/quartus_benchmark/test.qsf b/example_projects/quartus_benchmark/test.qsf new file mode 100755 index 0000000..e9237b0 --- /dev/null +++ b/example_projects/quartus_benchmark/test.qsf @@ -0,0 +1,22 @@ + +set_global_assignment -name FAMILY "Cyclone V" +set_global_assignment -name DEVICE 5CGXFC4C7F27C8 +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.0.0 +set_global_assignment -name LAST_QUARTUS_VERSION "17.0.0 Lite Edition" + +set_global_assignment -name TOP_LEVEL_ENTITY main +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY OUTPUT +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" +set_global_assignment -name POST_FLOW_SCRIPT_FILE "quartus_sh:post_flow.tcl" + +set_global_assignment -name SYSTEMVERILOG_FILE main.sv +set_global_assignment -name SYSTEMVERILOG_FILE dynamic_delay.sv +set_global_assignment -name SDC_FILE main.sdc + +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + + +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top