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Updated SR trigger variation modules

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This commit is contained in:
Konstantin Pavlov 2019-12-13 13:19:49 +03:00
parent 51f484b204
commit 21f4580a78
4 changed files with 144 additions and 10 deletions
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10
reset_set.sv
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@ -4,8 +4,8 @@
//--------------------------------------------------------------------------------
// INFO --------------------------------------------------------------------------------
// SR trigger variant
// No metastable state. SET dominates here
// Synchronous SR trigger variant
// No metastable state. SET signal dominates here
/* --- INSTANTIATION TEMPLATE BEGIN ---
@ -32,11 +32,11 @@ module reset_set(
);
always_ff @(posedge clk) begin
if (~nrst) begin
if( ~nrst ) begin
q = 0;
end else begin
if r q = 0;
if s q = 1;
if( r ) q = 1'b0;
if( s ) q = 1'b1;
end
end

67
reset_set_comb.sv Normal file
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@ -0,0 +1,67 @@
//--------------------------------------------------------------------------------
// reset_set_comb.sv
// Konstantin Pavlov, pavlovconst@gmail.com
//--------------------------------------------------------------------------------
// INFO --------------------------------------------------------------------------------
// Synchronous SR trigger, but has a combinational output that changes
// "with no delay" after inputs
// No metastable state. SET signal dominates here
// | | +---+ | | | | | | SET
// | | | | | | | | | |
// +------------+ +--------------------------------+
// | | | | | | | | | |
// | | | | | | +---+ | | RESET
// | | | | | | | | | |
// +----------------------------+ +----------------+
// | | | | | | | | | |
// | | | +---------------+ | | Q output, original
// | | | | | | | | | | reset_set.sv
// +----------------+ | | | +----------------+
// | | | | | | | | | |
// | | +---------------+ | | | Q output, this module
// | | | | | | | | | | reset_set_comb.sv
// +------------+ | | | +--------------------+
// | | | | | | | | | |
// | | | | | | | | | |
/* --- INSTANTIATION TEMPLATE BEGIN ---
reset_set_comb RS1 (
.clk( clk ),
.nrst( 1'b1 ),
.s( ),
.r( ),
.q( ),
.nq( )
);
--- INSTANTIATION TEMPLATE END ---*/
module reset_set_comb(
input clk,
input nrst,
input s,
input r,
output q,
output nq
);
logic q_reg = 0;
always_ff @(posedge clk) begin
if( ~nrst ) begin
q_reg = 0;
end else begin
if( r ) q_reg = 1'b0;
if( s ) q_reg = 1'b1;
end
end
assign q = s || (q_reg && ~r);
assign nq = ~q;
endmodule

10
set_reset.sv
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@ -4,8 +4,8 @@
//--------------------------------------------------------------------------------
// INFO --------------------------------------------------------------------------------
// SR trigger variant
// No metastable state. RESET dominates here
// Synchronous SR trigger variant
// No metastable state. RESET signal dominates here
/* --- INSTANTIATION TEMPLATE BEGIN ---
@ -32,11 +32,11 @@ module set_reset(
);
always_ff @(posedge clk) begin
if (~nrst) begin
if( ~nrst ) begin
q = 0;
end else begin
if s q = 1;
if r q = 0;
if( s ) q = 1'b1;
if( r ) q = 1'b0;
end
end

67
set_reset_comb.sv Normal file
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@ -0,0 +1,67 @@
//--------------------------------------------------------------------------------
// set_reset_comb.sv
// Konstantin Pavlov, pavlovconst@gmail.com
//--------------------------------------------------------------------------------
// INFO --------------------------------------------------------------------------------
// Synchronous SR trigger, but has a combinational output that changes
// "with no delay" after inputs
// No metastable state. RESET signal dominates here
// | | +---+ | | | | | | SET
// | | | | | | | | | |
// +------------+ +--------------------------------+
// | | | | | | | | | |
// | | | | | | +---+ | | RESET
// | | | | | | | | | |
// +----------------------------+ +----------------+
// | | | | | | | | | |
// | | | +---------------+ | | Q output, original
// | | | | | | | | | | set_reset.sv
// +----------------+ | | | +----------------+
// | | | | | | | | | |
// | | +---------------+ | | | Q output, this module
// | | | | | | | | | | set_reset_comb.sv
// +------------+ | | | +--------------------+
// | | | | | | | | | |
// | | | | | | | | | |
/* --- INSTANTIATION TEMPLATE BEGIN ---
set_reset_comb SR1 (
.clk( clk ),
.nrst( 1'b1 ),
.s( ),
.r( ),
.q( ),
.nq( )
);
--- INSTANTIATION TEMPLATE END ---*/
module set_reset_comb(
input clk,
input nrst,
input s,
input r,
output q,
output nq
);
logic q_reg = 0;
always_ff @(posedge clk) begin
if( ~nrst ) begin
q_reg = 0;
end else begin
if( s ) q_reg = 1'b1;
if( r ) q_reg = 1'b0;
end
end
assign q = (s || q_reg) && ~r;
assign nq = ~q;
endmodule